[llvm] [AMDGPU] Promote uniform ops to i32 in GISel (PR #106557)

[Matt Arsenault via llvm-commits]

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@@ -348,6 +351,112 @@ bool AMDGPURegBankCombinerImpl::matchFPMed3ToClamp(MachineInstr &MI,
   return false;
 }
 
+bool AMDGPURegBankCombinerImpl::matchPromote16to32(MachineInstr &MI) const {
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  const auto *RB = MRI.getRegBankOrNull(Dst);
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arsenm wrote:

Ideally would use RBI.getRegBank to handle the case where the register has a concrete register class. Failing that, this needs to return false on null 

https://github.com/llvm/llvm-project/pull/106557