[llvm] [AMDGPU] Promote uniform ops to i32 in GISel (PR #106557)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 24 04:00:58 PDT 2024
================
@@ -349,63 +349,67 @@ define amdgpu_ps <2 x i32> @s_orn2_v2i32_commute(<2 x i32> inreg %src0, <2 x i32
}
define amdgpu_ps i16 @s_orn2_i16(i16 inreg %src0, i16 inreg %src1) {
-; GCN-LABEL: s_orn2_i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_orn2_b32 s0, s2, s3
-; GCN-NEXT: ; return to shader part epilog
+; GFX6-LABEL: s_orn2_i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_orn2_b32 s0, s2, s3
+; GFX6-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_orn2_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_orn2_b32 s0, s2, s3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX9-LABEL: s_orn2_i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_xor_b32 s0, s3, -1
+; GFX9-NEXT: s_or_b32 s0, s2, s0
+; GFX9-NEXT: ; return to shader part epilog
----------------
arsenm wrote:
This is worse, the pattern is broken
https://github.com/llvm/llvm-project/pull/106557
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