[llvm] [RISCV] Don't create insert/extract subreg during lowering. (PR #109754)

[Fraser Cormack via llvm-commits]

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@@ -10304,8 +10304,11 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
         return Op;
       }
 
+      // Use a insert_subvector that will resolve to an insert subreg.
+      unsigned Vscale = *VLen / RISCV::RVVBitsPerBlock;
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frasercrmck wrote:

Do you think we should assert that `VLen` isn't zero? Some static analyzers might not like seeing a dangerous division. Given that we assert `VLen` earlier when `SubVecVT.isFixedLengthVector()` then perhaps it can work it out. Still, might be best to be explicit.

https://github.com/llvm/llvm-project/pull/109754