[llvm] 3659aa8 - [AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
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Tue Sep 24 02:11:49 PDT 2024
Author: Pravin Jagtap
Date: 2024-09-24T14:41:45+05:30
New Revision: 3659aa8079e00d7bd4f2d9c68c404a93ec297200
URL: https://github.com/llvm/llvm-project/commit/3659aa8079e00d7bd4f2d9c68c404a93ec297200
DIFF: https://github.com/llvm/llvm-project/commit/3659aa8079e00d7bd4f2d9c68c404a93ec297200.diff
LOG: [AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
Both SGPR->VGPR and VGPR->AGPR spilling code give a fixup to the spill
frame indices referred in debug instructions so that they can be
entirely removed. The stack argument is present at 0th index in
DBG_VALUE and at 2nd index for DBG_VALUE_LIST.
Fixes: SWDEV-484156
Added:
llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
Modified:
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 2c67c4aedfe475..50a6f028f66de6 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1418,10 +1418,15 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
// the debug value instructions. We should instead, update it with the
// correct register value. But not sure the register value alone is
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
- !MFI.isFixedObjectIndex(MI.getOperand(0).getIndex()) &&
- SpillFIs[MI.getOperand(0).getIndex()]) {
- MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
+ if (MI.isDebugValue()) {
+ uint32_t StackOperandIdx = MI.isDebugValueList() ? 2 : 0;
+ if (MI.getOperand(StackOperandIdx).isFI() &&
+ !MFI.isFixedObjectIndex(
+ MI.getOperand(StackOperandIdx).getIndex()) &&
+ SpillFIs[MI.getOperand(StackOperandIdx).getIndex()]) {
+ MI.getOperand(StackOperandIdx)
+ .ChangeToRegister(Register(), false /*isDef*/);
+ }
}
}
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 28bba8cfd73528..35e5bea9ae16e2 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -418,10 +418,15 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) {
// correct register value. But not sure the register value alone is
// adequate to lower the DIExpression. It should be worked out later.
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue() && MI.getOperand(0).isFI() &&
- !MFI.isFixedObjectIndex(MI.getOperand(0).getIndex()) &&
- SpillFIs[MI.getOperand(0).getIndex()]) {
- MI.getOperand(0).ChangeToRegister(Register(), false /*isDef*/);
+ if (MI.isDebugValue()) {
+ uint32_t StackOperandIdx = MI.isDebugValueList() ? 2 : 0;
+ if (MI.getOperand(StackOperandIdx).isFI() &&
+ !MFI.isFixedObjectIndex(
+ MI.getOperand(StackOperandIdx).getIndex()) &&
+ SpillFIs[MI.getOperand(StackOperandIdx).getIndex()]) {
+ MI.getOperand(StackOperandIdx)
+ .ChangeToRegister(Register(), false /*isDef*/);
+ }
}
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
new file mode 100644
index 00000000000000..cdf2b41c1e5b45
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
@@ -0,0 +1,53 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
+
+--- |
+ define amdgpu_kernel void @test() { ret void }
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
+ !1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
+ !2 = distinct !DISubprogram(name: "test", scope: !4, file: !4, line: 1, type: !3, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !5)
+ !3 = !DISubroutineType(types: !4)
+ !4 = !DIFile(filename: "dummy", directory: "/")
+ !5 = !{!1}
+ !6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64, align: 32)
+ !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+ !8 = !DIExpression()
+ !9 = !DILocation(line: 10, column: 9, scope: !2)
+
+...
+---
+name: test
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 4
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default }
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+machineFunctionInfo:
+ maxKernArgAlign: 4
+ isEntryFunction: true
+ waveLimiter: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+ frameOffsetReg: '$sgpr33'
+ hasSpilledSGPRs: true
+ argumentInfo:
+ privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+ dispatchPtr: { reg: '$sgpr4_sgpr5' }
+ kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
+ workGroupIDX: { reg: '$sgpr8' }
+ privateSegmentWaveByteOffset: { reg: '$sgpr9' }
+body: |
+ ; CHECK-LABEL: name: test
+ ; CHECK: bb.0:
+ ; CHECK: DBG_VALUE_LIST <{{.*}}>, !DIExpression(), $noreg, 0, debug-location !DILocation(line: 10, column: 9, scope: <{{.*}}>)
+
+ bb.0:
+ renamable $sgpr10 = IMPLICIT_DEF
+ SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
+ DBG_VALUE_LIST !1, !8, %stack.0, 0, debug-location !9
+
+ bb.1:
+ renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
+ S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
new file mode 100644
index 00000000000000..53629cdfb932b2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
@@ -0,0 +1,52 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -run-pass=prologepilog -o - %s | FileCheck %s
+
+--- |
+ define amdgpu_kernel void @test() { ret void }
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
+ !1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
+ !2 = distinct !DISubprogram(name: "test", scope: !4, file: !4, line: 1, type: !3, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !5)
+ !3 = !DISubroutineType(types: !4)
+ !4 = !DIFile(filename: "dummy", directory: "/")
+ !5 = !{!1}
+ !6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64, align: 32)
+ !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+ !8 = !DIExpression()
+ !9 = !DILocation(line: 10, column: 9, scope: !2)
+
+...
+---
+name: test
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 4
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default }
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4 }
+machineFunctionInfo:
+ maxKernArgAlign: 4
+ isEntryFunction: true
+ waveLimiter: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+ frameOffsetReg: '$sgpr33'
+ hasSpilledVGPRs: true
+ argumentInfo:
+ privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+ dispatchPtr: { reg: '$sgpr4_sgpr5' }
+ kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
+ workGroupIDX: { reg: '$sgpr8' }
+ privateSegmentWaveByteOffset: { reg: '$sgpr9' }
+body: |
+ ; CHECK-LABEL: name: test
+ ; CHECK: bb.0:
+ ; CHECK: DBG_VALUE_LIST <{{.*}}>, !DIExpression(), $noreg, 0, debug-location !DILocation(line: 10, column: 9, scope: <{{.*}}>)
+ bb.0:
+ $vgpr2 = IMPLICIT_DEF
+ SI_SPILL_V32_SAVE $vgpr2, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, align 4, addrspace 5)
+ DBG_VALUE_LIST !1, !8, %stack.0, 0, debug-location !9
+
+ bb.1:
+ renamable $vgpr2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, align 4, addrspace 5)
+ S_ENDPGM 0
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