[llvm] 9d3a576 - [RISCV] Add explicit XLenVT cast to vector load/store patterns.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-09-23T16:02:58-07:00
New Revision: 9d3a57633ebb8251d2575696dfe53c67d3a47d33

URL: https://github.com/llvm/llvm-project/commit/9d3a57633ebb8251d2575696dfe53c67d3a47d33
DIFF: https://github.com/llvm/llvm-project/commit/9d3a57633ebb8251d2575696dfe53c67d3a47d33.diff

LOG: [RISCV] Add explicit XLenVT cast to vector load/store patterns.

This seems to be needed to get the patterns to import into GISel
properly.

Unfortunately, it also adds ~400 bytes to the SelectionDAG table.
I'm hoping if we remove i32 as a legal type for GPR registers, this
will go down.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index b54cdcbd1b0e9c..0df0187d40889b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -33,11 +33,11 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
   defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
   defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
   // Load
-  def : Pat<(type (load GPR:$rs1)),
+  def : Pat<(type (load (XLenVT GPR:$rs1))),
             (load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
                         log2sew, TA_MA)>;
   // Store
-  def : Pat<(store type:$rs2, GPR:$rs1),
+  def : Pat<(store type:$rs2, (XLenVT GPR:$rs1)),
             (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
 }