[llvm] [llvm] use 64-bit types for result of getDwarfRegNum (NFC) (PR #109494)

[William G Hatch via llvm-commits]

================
@@ -151,24 +151,28 @@ int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
   const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
   if (I == M+Size || I->FromReg != RegNum)
     return -1;
-  return I->ToReg;
+  // Consumers need to be able to detect -1 and -2, but at various points
+  // the numbers move between unsigned and signed representations, as well as
+  // between 32- and 64-bit representations. We need to convert first to int
+  // before int64_t for proper sign handling.
+  return int64_t(int(I->ToReg));
 }
 
-std::optional<MCRegister> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
+std::optional<MCRegister> MCRegisterInfo::getLLVMRegNum(uint64_t RegNum,
                                                         bool isEH) const {
   const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
   unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
 
   if (!M)
     return std::nullopt;
-  DwarfLLVMRegPair Key = { RegNum, 0 };
+  DwarfLLVMRegPair Key = {unsigned(RegNum), 0};
----------------
willghatch wrote:

I originally tried to do a broader switch to 64-bit types for registers, but it caused many problems.  There are various places in code generation where registers are not just treated as 32-bit numbers, but also treat certain bit offsets as flags.  So I limited the change as much as possible to just the output of `getDwarfRegNum`.  Keeping the types used by `DwarfLLVMRegPair` as `unsigned` preserves the current behaviors.  The only way to give a 64-bit output from `getDwarfRegNum` that actually needs more than 32-bits is to override `getDwarfRegNum` and provide an implementation that sidesteps these maps.  These maps are generated from tablegen register definitions, and don't make sense for an implementation that needs to use a weird encoding that requires 64 bits anyway.

https://github.com/llvm/llvm-project/pull/109494