[llvm] llvm-reduce: Don't print verifier failed machine functions (PR #109673)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 23 11:24:31 PDT 2024
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/109673
>From 356cba3a14405771ac0dd32f8e15d3bd536f85d7 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 22 Apr 2022 17:50:51 -0400
Subject: [PATCH 1/2] llvm-reduce: Don't print verifier failed machine
functions
This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness of of
the instructions it's deleting, it produces quite a lot of verifier
errors.
---
llvm/include/llvm/CodeGen/MachineFunction.h | 2 +-
llvm/lib/CodeGen/MachineVerifier.cpp | 33 +++++++++++++--------
llvm/tools/llvm-reduce/ReducerWorkItem.cpp | 6 +++-
3 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index aeb72ca24d79b8..d91ce8067c24ae 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -897,7 +897,7 @@ class LLVM_ABI MachineFunction {
/// for debugger use.
/// \returns true if no problems were found.
bool verify(Pass *p = nullptr, const char *Banner = nullptr,
- bool AbortOnError = true) const;
+ bool AbortOnError = true, bool PrintFuncOnError = true) const;
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 27664207d1e696..d155d51ee18791 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -94,16 +94,18 @@ using namespace llvm;
namespace {
struct MachineVerifier {
- MachineVerifier(MachineFunctionAnalysisManager &MFAM, const char *b)
- : MFAM(&MFAM), Banner(b) {}
+ MachineVerifier(MachineFunctionAnalysisManager &MFAM, const char *b,
+ bool PrintFuncOnError = true)
+ : MFAM(&MFAM), Banner(b), PrintFuncOnError(PrintFuncOnError) {}
- MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
+ MachineVerifier(Pass *pass, const char *b, bool PrintFuncOnError = true)
+ : PASS(pass), Banner(b), PrintFuncOnError(PrintFuncOnError) {}
MachineVerifier(const char *b, LiveVariables *LiveVars,
LiveIntervals *LiveInts, LiveStacks *LiveStks,
- SlotIndexes *Indexes)
- : Banner(b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
- Indexes(Indexes) {}
+ SlotIndexes *Indexes, bool PrintFuncOnError = true)
+ : Banner(b), PrintFuncOnError(PrintFuncOnError), LiveVars(LiveVars),
+ LiveInts(LiveInts), LiveStks(LiveStks), Indexes(Indexes) {}
unsigned verify(const MachineFunction &MF);
@@ -118,6 +120,7 @@ namespace {
const RegisterBankInfo *RBI = nullptr;
unsigned foundErrors = 0;
+ bool PrintFuncOnError = false;
// Avoid querying the MachineFunctionProperties for each operand.
bool isFunctionRegBankSelected = false;
@@ -379,10 +382,11 @@ void llvm::verifyMachineFunction(const std::string &Banner,
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
}
-bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
- const {
+bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors,
+ bool PrintFuncOnError) const {
MachineFunction &MF = const_cast<MachineFunction&>(*this);
- unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(p, Banner, PrintFuncOnError).verify(MF);
if (AbortOnErrors && FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
return FoundErrors == 0;
@@ -544,10 +548,13 @@ void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
if (!foundErrors++) {
if (Banner)
errs() << "# " << Banner << '\n';
- if (LiveInts != nullptr)
- LiveInts->print(errs());
- else
- MF->print(errs(), Indexes);
+
+ if (PrintFuncOnError) {
+ if (LiveInts != nullptr)
+ LiveInts->print(errs());
+ else
+ MF->print(errs(), Indexes);
+ }
}
errs() << "*** Bad machine code: " << msg << " ***\n"
<< "- function: " << MF->getName() << "\n";
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 1510e9fb32007e..6ccfaff8fa3e15 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -450,7 +450,11 @@ bool ReducerWorkItem::verify(raw_fd_ostream *OS) const {
for (const Function &F : getModule()) {
if (const MachineFunction *MF = MMI->getMachineFunction(F)) {
- if (!MF->verify(nullptr, "", /*AbortOnError=*/false))
+ // With the current state of quality, most reduction attempts fail the
+ // machine verifier. Avoid spamming large function dumps on nearly every
+ // attempt until the situation is better.
+ if (!MF->verify(nullptr, "", /*AbortOnError=*/false,
+ /*PrintFuncOnError=*/false))
return true;
}
}
>From 799fcb452be71bcc50466703332d089363dde309 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 23 Sep 2024 21:10:24 +0400
Subject: [PATCH 2/2] Pass output stream
---
llvm/include/llvm/CodeGen/MachineFunction.h | 5 +-
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 +-
llvm/lib/CodeGen/MachineBlockPlacement.cpp | 2 +-
llvm/lib/CodeGen/MachineScheduler.cpp | 8 +-
llvm/lib/CodeGen/MachineVerifier.cpp | 231 ++++++++++----------
llvm/lib/CodeGen/RegAllocGreedy.cpp | 10 +-
llvm/lib/CodeGen/RegisterCoalescer.cpp | 4 +-
llvm/tools/llvm-reduce/ReducerWorkItem.cpp | 6 +-
llvm/unittests/MI/LiveIntervalTest.cpp | 4 +-
9 files changed, 138 insertions(+), 134 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index d91ce8067c24ae..5c1da4fa762e84 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -897,13 +897,14 @@ class LLVM_ABI MachineFunction {
/// for debugger use.
/// \returns true if no problems were found.
bool verify(Pass *p = nullptr, const char *Banner = nullptr,
- bool AbortOnError = true, bool PrintFuncOnError = true) const;
+ raw_ostream *OS = nullptr, bool AbortOnError = true) const;
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
- const char *Banner = nullptr, bool AbortOnError = true) const;
+ const char *Banner = nullptr, raw_ostream *OS = nullptr,
+ bool AbortOnError = true) const;
// Provide accessors for the MachineBasicBlock list...
using iterator = BasicBlockListType::iterator;
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index d506cd1879648f..947344e3ea775c 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -604,7 +604,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
MF.getSubtarget().mirFileLoaded(MF);
- MF.verify();
+ MF.verify(nullptr, nullptr, &errs());
return false;
}
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index be783bc4e29738..99254c710b3012 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -3705,7 +3705,7 @@ void MachineBlockPlacement::assignBlockOrder(
#ifndef NDEBUG
// Make sure we correctly constructed all branches.
- F->verify(this, "After optimized block reordering");
+ F->verify(this, "After optimized block reordering", &errs());
#endif
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 4e6d34346b1d80..9b2862de22b690 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -453,7 +453,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (VerifyScheduling) {
LLVM_DEBUG(LIS->dump());
- MF->verify(this, "Before machine scheduling.");
+ MF->verify(this, "Before machine scheduling.", &errs());
}
RegClassInfo->runOnMachineFunction(*MF);
@@ -472,7 +472,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
LLVM_DEBUG(LIS->dump());
if (VerifyScheduling)
- MF->verify(this, "After machine scheduling.");
+ MF->verify(this, "After machine scheduling.", &errs());
return true;
}
@@ -496,7 +496,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
if (VerifyScheduling)
- MF->verify(this, "Before post machine scheduling.");
+ MF->verify(this, "Before post machine scheduling.", &errs());
// Instantiate the selected scheduler for this target, function, and
// optimization level.
@@ -512,7 +512,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
scheduleRegions(*Scheduler, true);
if (VerifyScheduling)
- MF->verify(this, "After post machine scheduling.");
+ MF->verify(this, "After post machine scheduling.", &errs());
return true;
}
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index d155d51ee18791..359cf04034ecab 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -95,22 +95,23 @@ namespace {
struct MachineVerifier {
MachineVerifier(MachineFunctionAnalysisManager &MFAM, const char *b,
- bool PrintFuncOnError = true)
- : MFAM(&MFAM), Banner(b), PrintFuncOnError(PrintFuncOnError) {}
+ raw_ostream *OS)
+ : MFAM(&MFAM), OS(OS ? OS : &nulls()), Banner(b) {}
- MachineVerifier(Pass *pass, const char *b, bool PrintFuncOnError = true)
- : PASS(pass), Banner(b), PrintFuncOnError(PrintFuncOnError) {}
+ MachineVerifier(Pass *pass, const char *b, raw_ostream *OS)
+ : PASS(pass), OS(OS ? OS : &nulls()), Banner(b) {}
MachineVerifier(const char *b, LiveVariables *LiveVars,
LiveIntervals *LiveInts, LiveStacks *LiveStks,
- SlotIndexes *Indexes, bool PrintFuncOnError = true)
- : Banner(b), PrintFuncOnError(PrintFuncOnError), LiveVars(LiveVars),
+ SlotIndexes *Indexes, raw_ostream *OS)
+ : OS(OS ? OS : &nulls()), Banner(b), LiveVars(LiveVars),
LiveInts(LiveInts), LiveStks(LiveStks), Indexes(Indexes) {}
unsigned verify(const MachineFunction &MF);
MachineFunctionAnalysisManager *MFAM = nullptr;
Pass *const PASS = nullptr;
+ raw_ostream *OS = nullptr;
const char *Banner;
const MachineFunction *MF = nullptr;
const TargetMachine *TM = nullptr;
@@ -120,7 +121,6 @@ namespace {
const RegisterBankInfo *RBI = nullptr;
unsigned foundErrors = 0;
- bool PrintFuncOnError = false;
// Avoid querying the MachineFunctionProperties for each operand.
bool isFunctionRegBankSelected = false;
@@ -337,7 +337,8 @@ namespace {
MachineFunctionProperties::Property::FailsVerification))
return false;
- unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(this, Banner.c_str(), &errs()).verify(MF);
if (FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
return false;
@@ -355,7 +356,8 @@ MachineVerifierPass::run(MachineFunction &MF,
if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::FailsVerification))
return PreservedAnalyses::all();
- unsigned FoundErrors = MachineVerifier(MFAM, Banner.c_str()).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(MFAM, Banner.c_str(), &errs()).verify(MF);
if (FoundErrors)
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
return PreservedAnalyses::all();
@@ -377,26 +379,28 @@ void llvm::verifyMachineFunction(const std::string &Banner,
// LiveIntervals *LiveInts;
// LiveStacks *LiveStks;
// SlotIndexes *Indexes;
- unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
+ unsigned FoundErrors =
+ MachineVerifier(nullptr, Banner.c_str(), &errs()).verify(MF);
if (FoundErrors)
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
}
-bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors,
- bool PrintFuncOnError) const {
+bool MachineFunction::verify(Pass *p, const char *Banner, raw_ostream *OS,
+ bool AbortOnErrors) const {
MachineFunction &MF = const_cast<MachineFunction&>(*this);
- unsigned FoundErrors =
- MachineVerifier(p, Banner, PrintFuncOnError).verify(MF);
+ unsigned FoundErrors = MachineVerifier(p, Banner, OS).verify(MF);
if (AbortOnErrors && FoundErrors)
report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
return FoundErrors == 0;
}
bool MachineFunction::verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
- const char *Banner, bool AbortOnErrors) const {
+ const char *Banner, raw_ostream *OS,
+ bool AbortOnErrors) const {
MachineFunction &MF = const_cast<MachineFunction &>(*this);
unsigned FoundErrors =
- MachineVerifier(Banner, nullptr, LiveInts, nullptr, Indexes).verify(MF);
+ MachineVerifier(Banner, nullptr, LiveInts, nullptr, Indexes, OS)
+ .verify(MF);
if (AbortOnErrors && FoundErrors)
report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
return FoundErrors == 0;
@@ -486,7 +490,7 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
for (const MachineInstr &MI : MBB.instrs()) {
if (MI.getParent() != &MBB) {
report("Bad instruction parent pointer", &MBB);
- errs() << "Instruction: " << MI;
+ *OS << "Instruction: " << MI;
continue;
}
@@ -544,49 +548,48 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
assert(MF);
- errs() << '\n';
+ *OS << '\n';
if (!foundErrors++) {
if (Banner)
- errs() << "# " << Banner << '\n';
+ *OS << "# " << Banner << '\n';
- if (PrintFuncOnError) {
- if (LiveInts != nullptr)
- LiveInts->print(errs());
- else
- MF->print(errs(), Indexes);
- }
+ if (LiveInts != nullptr)
+ LiveInts->print(*OS);
+ else
+ MF->print(*OS, Indexes);
}
- errs() << "*** Bad machine code: " << msg << " ***\n"
- << "- function: " << MF->getName() << "\n";
+
+ *OS << "*** Bad machine code: " << msg << " ***\n"
+ << "- function: " << MF->getName() << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
assert(MBB);
report(msg, MBB->getParent());
- errs() << "- basic block: " << printMBBReference(*MBB) << ' '
- << MBB->getName() << " (" << (const void *)MBB << ')';
+ *OS << "- basic block: " << printMBBReference(*MBB) << ' ' << MBB->getName()
+ << " (" << (const void *)MBB << ')';
if (Indexes)
- errs() << " [" << Indexes->getMBBStartIdx(MBB)
- << ';' << Indexes->getMBBEndIdx(MBB) << ')';
- errs() << '\n';
+ *OS << " [" << Indexes->getMBBStartIdx(MBB) << ';'
+ << Indexes->getMBBEndIdx(MBB) << ')';
+ *OS << '\n';
}
void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
assert(MI);
report(msg, MI->getParent());
- errs() << "- instruction: ";
+ *OS << "- instruction: ";
if (Indexes && Indexes->hasIndex(*MI))
- errs() << Indexes->getInstructionIndex(*MI) << '\t';
- MI->print(errs(), /*IsStandalone=*/true);
+ *OS << Indexes->getInstructionIndex(*MI) << '\t';
+ MI->print(*OS, /*IsStandalone=*/true);
}
void MachineVerifier::report(const char *msg, const MachineOperand *MO,
unsigned MONum, LLT MOVRegType) {
assert(MO);
report(msg, MO->getParent());
- errs() << "- operand " << MONum << ": ";
- MO->print(errs(), MOVRegType, TRI);
- errs() << "\n";
+ *OS << "- operand " << MONum << ": ";
+ MO->print(*OS, MOVRegType, TRI);
+ *OS << '\n';
}
void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
@@ -594,11 +597,11 @@ void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
}
void MachineVerifier::report_context(SlotIndex Pos) const {
- errs() << "- at: " << Pos << '\n';
+ *OS << "- at: " << Pos << '\n';
}
void MachineVerifier::report_context(const LiveInterval &LI) const {
- errs() << "- interval: " << LI << '\n';
+ *OS << "- interval: " << LI << '\n';
}
void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
@@ -610,35 +613,35 @@ void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
}
void MachineVerifier::report_context(const LiveRange::Segment &S) const {
- errs() << "- segment: " << S << '\n';
+ *OS << "- segment: " << S << '\n';
}
void MachineVerifier::report_context(const VNInfo &VNI) const {
- errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
+ *OS << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
}
void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
- errs() << "- liverange: " << LR << '\n';
+ *OS << "- liverange: " << LR << '\n';
}
void MachineVerifier::report_context(MCPhysReg PReg) const {
- errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
+ *OS << "- p. register: " << printReg(PReg, TRI) << '\n';
}
void MachineVerifier::report_context_vreg(Register VReg) const {
- errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
+ *OS << "- v. register: " << printReg(VReg, TRI) << '\n';
}
void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
if (VRegOrUnit.isVirtual()) {
report_context_vreg(VRegOrUnit);
} else {
- errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
+ *OS << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
}
}
void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
- errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
+ *OS << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
}
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
@@ -717,8 +720,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
report("MBB has successor that isn't part of the function.", MBB);
if (!MBBInfoMap[succ].Preds.count(MBB)) {
report("Inconsistent CFG", MBB);
- errs() << "MBB is not in the predecessor list of the successor "
- << printMBBReference(*succ) << ".\n";
+ *OS << "MBB is not in the predecessor list of the successor "
+ << printMBBReference(*succ) << ".\n";
}
}
@@ -728,8 +731,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
report("MBB has predecessor that isn't part of the function.", MBB);
if (!MBBInfoMap[Pred].Succs.count(MBB)) {
report("Inconsistent CFG", MBB);
- errs() << "MBB is not in the successor list of the predecessor "
- << printMBBReference(*Pred) << ".\n";
+ *OS << "MBB is not in the successor list of the predecessor "
+ << printMBBReference(*Pred) << ".\n";
}
}
@@ -887,7 +890,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
SlotIndex idx = Indexes->getInstructionIndex(*MI);
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
- errs() << "Last instruction was at " << lastIndex << '\n';
+ *OS << "Last instruction was at " << lastIndex << '\n';
}
lastIndex = idx;
}
@@ -901,7 +904,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
// precede non-terminators.
if (FirstTerminator->getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
report("Non-terminator instruction after the first terminator", MI);
- errs() << "First terminator was:\t" << *FirstTerminator;
+ *OS << "First terminator was:\t" << *FirstTerminator;
}
}
}
@@ -2192,8 +2195,8 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
const MCInstrDesc &MCID = MI->getDesc();
if (MI->getNumOperands() < MCID.getNumOperands()) {
report("Too few operands", MI);
- errs() << MCID.getNumOperands() << " operands expected, but "
- << MI->getNumOperands() << " given.\n";
+ *OS << MCID.getNumOperands() << " operands expected, but "
+ << MI->getNumOperands() << " given.\n";
}
if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent())
@@ -2285,7 +2288,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
// If both types are valid, check that the types are the same.
if (SrcTy != DstTy) {
report("Copy Instruction is illegal with mismatching types", MI);
- errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
+ *OS << "Def = " << DstTy << ", Src = " << SrcTy << '\n';
}
break;
@@ -2329,8 +2332,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
if (SrcSize.isNonZero() && DstSize.isNonZero() && SrcSize != DstSize) {
if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
report("Copy Instruction is illegal with mismatching sizes", MI);
- errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
- << "\n";
+ *OS << "Def Size = " << DstSize << ", Src Size = " << SrcSize << '\n';
}
}
break;
@@ -2561,8 +2563,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (!DRC->contains(Reg)) {
report("Illegal physical register for instruction", MO, MONum);
- errs() << printReg(Reg, TRI) << " is not a "
- << TRI->getRegClassName(DRC) << " register.\n";
+ *OS << printReg(Reg, TRI) << " is not a "
+ << TRI->getRegClassName(DRC) << " register.\n";
}
}
}
@@ -2625,9 +2627,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
report("Register bank is too small for virtual register", MO,
MONum);
- errs() << "Register bank " << RegBank->getName() << " too small("
- << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
- << Ty.getSizeInBits() << "-bits\n";
+ *OS << "Register bank " << RegBank->getName() << " too small("
+ << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
+ << Ty.getSizeInBits() << "-bits\n";
return;
}
}
@@ -2646,10 +2648,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TII->getRegClass(MCID, MONum, TRI, *MF)) {
report("Virtual register does not match instruction constraint", MO,
MONum);
- errs() << "Expect register class "
- << TRI->getRegClassName(
- TII->getRegClass(MCID, MONum, TRI, *MF))
- << " but got nothing\n";
+ *OS << "Expect register class "
+ << TRI->getRegClassName(TII->getRegClass(MCID, MONum, TRI, *MF))
+ << " but got nothing\n";
return;
}
@@ -2660,14 +2661,14 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TRI->getSubClassWithSubReg(RC, SubIdx);
if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
- errs() << "Register class " << TRI->getRegClassName(RC)
- << " does not support subreg index " << SubIdx << "\n";
+ *OS << "Register class " << TRI->getRegClassName(RC)
+ << " does not support subreg index " << SubIdx << '\n';
return;
}
if (RC != SRC) {
report("Invalid register class for subregister index", MO, MONum);
- errs() << "Register class " << TRI->getRegClassName(RC)
- << " does not fully support subreg index " << SubIdx << "\n";
+ *OS << "Register class " << TRI->getRegClassName(RC)
+ << " does not fully support subreg index " << SubIdx << '\n';
return;
}
}
@@ -2689,7 +2690,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
if (!RC->hasSuperClassEq(DRC)) {
report("Illegal virtual register for instruction", MO, MONum);
- errs() << "Expected a " << TRI->getRegClassName(DRC)
+ *OS << "Expected a " << TRI->getRegClassName(DRC)
<< " register, but got a " << TRI->getRegClassName(RC)
<< " register\n";
}
@@ -2740,11 +2741,11 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
report("Instruction loads from dead spill slot", MO, MONum);
- errs() << "Live stack: " << LI << '\n';
+ *OS << "Live stack: " << LI << '\n';
}
if (stores && !LI.liveAt(Idx.getRegSlot())) {
report("Instruction stores to dead spill slot", MO, MONum);
- errs() << "Live stack: " << LI << '\n';
+ *OS << "Live stack: " << LI << '\n';
}
}
break;
@@ -3039,8 +3040,8 @@ MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
SlotIndex stop = Indexes->getMBBEndIdx(MBB);
if (!(stop > lastIndex)) {
report("Block ends before last instruction index", MBB);
- errs() << "Block ends at " << stop
- << " last instruction was at " << lastIndex << '\n';
+ *OS << "Block ends at " << stop << " last instruction was at "
+ << lastIndex << '\n';
}
lastIndex = stop;
}
@@ -3285,8 +3286,8 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
for (MachineBasicBlock *Pred : MBB.predecessors()) {
if (!seen.count(Pred)) {
report("Missing PHI operand", &Phi);
- errs() << printMBBReference(*Pred)
- << " is a predecessor according to the CFG.\n";
+ *OS << printMBBReference(*Pred)
+ << " is a predecessor according to the CFG.\n";
}
}
}
@@ -3295,9 +3296,10 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
static void
verifyConvergenceControl(const MachineFunction &MF, MachineDominatorTree &DT,
- std::function<void(const Twine &Message)> FailureCB) {
+ std::function<void(const Twine &Message)> FailureCB,
+ raw_ostream *OS) {
MachineConvergenceVerifier CV;
- CV.initialize(&errs(), FailureCB, MF);
+ CV.initialize(OS, FailureCB, MF);
for (const auto &MBB : MF) {
CV.visit(MBB);
@@ -3315,7 +3317,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
auto FailureCB = [this](const Twine &Message) {
report(Message.str().c_str(), MF);
};
- verifyConvergenceControl(*MF, DT, FailureCB);
+ verifyConvergenceControl(*MF, DT, FailureCB, OS);
calcRegsPassed();
@@ -3331,8 +3333,8 @@ void MachineVerifier::visitMachineFunctionAfter() {
for (Register VReg : MInfo.vregsRequired)
if (MInfo.regsKilled.count(VReg)) {
report("Virtual register killed in block, but needed live out.", &MBB);
- errs() << "Virtual register " << printReg(VReg)
- << " is used after the block.\n";
+ *OS << "Virtual register " << printReg(VReg)
+ << " is used after the block.\n";
}
}
@@ -3368,9 +3370,8 @@ void MachineVerifier::visitMachineFunctionAfter() {
if (!PInfo.regsLiveOut.count(LiveInReg)) {
report("Live in register not found to be live out from predecessor.",
&MBB);
- errs() << TRI->getName(LiveInReg)
- << " not found to be live out from "
- << printMBBReference(*Pred) << "\n";
+ *OS << TRI->getName(LiveInReg) << " not found to be live out from "
+ << printMBBReference(*Pred) << '\n';
}
}
}
@@ -3407,14 +3408,14 @@ void MachineVerifier::verifyLiveVariables() {
if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB);
- errs() << "Virtual register " << printReg(Reg)
- << " must be live through the block.\n";
+ *OS << "Virtual register " << printReg(Reg)
+ << " must be live through the block.\n";
}
} else {
if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB);
- errs() << "Virtual register " << printReg(Reg)
- << " is not needed live through the block.\n";
+ *OS << "Virtual register " << printReg(Reg)
+ << " is not needed live through the block.\n";
}
}
}
@@ -3432,7 +3433,7 @@ void MachineVerifier::verifyLiveIntervals() {
if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF);
- errs() << printReg(Reg, TRI) << " still has defs or uses\n";
+ *OS << printReg(Reg, TRI) << " still has defs or uses\n";
continue;
}
@@ -3744,9 +3745,9 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
report("Register not marked live out of predecessor", Pred);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
- errs() << " live into " << printMBBReference(*MFI) << '@'
- << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
- << PEnd << '\n';
+ *OS << " live into " << printMBBReference(*MFI) << '@'
+ << LiveInts->getMBBStartIdx(&*MFI) << ", not live before " << PEnd
+ << '\n';
continue;
}
@@ -3754,10 +3755,10 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
if (!IsPHI && PVNI != VNI) {
report("Different value live out of predecessor", Pred);
report_context(LR, Reg, LaneMask);
- errs() << "Valno #" << PVNI->id << " live out of "
- << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
- << VNI->id << " live into " << printMBBReference(*MFI) << '@'
- << LiveInts->getMBBStartIdx(&*MFI) << '\n';
+ *OS << "Valno #" << PVNI->id << " live out of "
+ << printMBBReference(*Pred) << '@' << PEnd << "\nValno #" << VNI->id
+ << " live into " << printMBBReference(*MFI) << '@'
+ << LiveInts->getMBBStartIdx(&*MFI) << '\n';
}
}
if (&*MFI == EndMBB)
@@ -3812,11 +3813,11 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
report("Multiple connected components in live interval", MF);
report_context(LI);
for (unsigned comp = 0; comp != NumComp; ++comp) {
- errs() << comp << ": valnos";
+ *OS << comp << ": valnos";
for (const VNInfo *I : LI.valnos)
if (comp == ConEQ.getEqClass(I))
- errs() << ' ' << I->id;
- errs() << '\n';
+ *OS << ' ' << I->id;
+ *OS << '\n';
}
}
}
@@ -3878,9 +3879,9 @@ void MachineVerifier::verifyStackFrame() {
report("Call frame size on entry does not match value computed from "
"predecessor",
MBB);
- errs() << "Call frame size on entry " << MBB->getCallFrameSize()
- << " does not match value computed from predecessor "
- << -BBState.EntryValue << '\n';
+ *OS << "Call frame size on entry " << MBB->getCallFrameSize()
+ << " does not match value computed from predecessor "
+ << -BBState.EntryValue << '\n';
}
// Update stack state by checking contents of MBB.
@@ -3903,7 +3904,7 @@ void MachineVerifier::verifyStackFrame() {
BBState.ExitValue;
if (BBState.ExitIsSetup && AbsSPAdj != Size) {
report("FrameDestroy <n> is after FrameSetup <m>", &I);
- errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
+ *OS << "FrameDestroy <" << Size << "> is after FrameSetup <"
<< AbsSPAdj << ">.\n";
}
if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
@@ -3922,11 +3923,11 @@ void MachineVerifier::verifyStackFrame() {
(SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
report("The exit stack state of a predecessor is inconsistent.", MBB);
- errs() << "Predecessor " << printMBBReference(*Pred)
- << " has exit state (" << SPState[Pred->getNumber()].ExitValue
- << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
- << printMBBReference(*MBB) << " has entry state ("
- << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
+ *OS << "Predecessor " << printMBBReference(*Pred) << " has exit state ("
+ << SPState[Pred->getNumber()].ExitValue << ", "
+ << SPState[Pred->getNumber()].ExitIsSetup << "), while "
+ << printMBBReference(*MBB) << " has entry state ("
+ << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
}
}
@@ -3937,11 +3938,11 @@ void MachineVerifier::verifyStackFrame() {
(SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
report("The entry stack state of a successor is inconsistent.", MBB);
- errs() << "Successor " << printMBBReference(*Succ)
- << " has entry state (" << SPState[Succ->getNumber()].EntryValue
- << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
- << printMBBReference(*MBB) << " has exit state ("
- << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
+ *OS << "Successor " << printMBBReference(*Succ) << " has entry state ("
+ << SPState[Succ->getNumber()].EntryValue << ", "
+ << SPState[Succ->getNumber()].EntryIsSetup << "), while "
+ << printMBBReference(*MBB) << " has exit state ("
+ << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
}
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 5001b4fec58f2e..1ad70c86d68e3d 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -1054,7 +1054,7 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around region");
+ MF->verify(this, "After splitting live range around region", &errs());
}
MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg,
@@ -1323,7 +1323,7 @@ unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around basic blocks");
+ MF->verify(this, "After splitting live range around basic blocks", &errs());
return 0;
}
@@ -2507,7 +2507,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
DebugVars->splitRegister(VirtReg.reg(), LRE.regs(), *LIS);
if (VerifyEnabled)
- MF->verify(this, "After spilling");
+ MF->verify(this, "After spilling", &errs());
}
// The live virtual register requesting allocation was spilled, so tell
@@ -2711,7 +2711,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
TII = MF->getSubtarget().getInstrInfo();
if (VerifyEnabled)
- MF->verify(this, "Before greedy register allocator");
+ MF->verify(this, "Before greedy register allocator", &errs());
RegAllocBase::init(getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
@@ -2770,7 +2770,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
tryHintsRecoloring();
if (VerifyEnabled)
- MF->verify(this, "Before post optimization");
+ MF->verify(this, "Before post optimization", &errs());
postOptimization();
reportStats();
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 97f8346df0e8fe..be2a6de4fe1430 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -4240,7 +4240,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
JoinSplitEdges = EnableJoinSplits;
if (VerifyCoalescing)
- MF->verify(this, "Before register coalescing");
+ MF->verify(this, "Before register coalescing", &errs());
DbgVRegToValues.clear();
buildVRegToDbgValueMap(fn);
@@ -4300,7 +4300,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
LLVM_DEBUG(dump());
if (VerifyCoalescing)
- MF->verify(this, "After register coalescing");
+ MF->verify(this, "After register coalescing", &errs());
return true;
}
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 6ccfaff8fa3e15..c1eefd5451fa07 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -417,7 +417,7 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF,
DstMRI->freezeReservedRegs();
- DstMF->verify(nullptr, "", /*AbortOnError=*/true);
+ DstMF->verify(nullptr, "", &errs(), /*AbortOnError=*/true);
return DstMF;
}
@@ -453,8 +453,8 @@ bool ReducerWorkItem::verify(raw_fd_ostream *OS) const {
// With the current state of quality, most reduction attempts fail the
// machine verifier. Avoid spamming large function dumps on nearly every
// attempt until the situation is better.
- if (!MF->verify(nullptr, "", /*AbortOnError=*/false,
- /*PrintFuncOnError=*/false))
+ if (!MF->verify(nullptr, "", /*OS=*/nullptr,
+ /*AbortOnError=*/false))
return true;
}
}
diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp
index 7dcd82f3e7aa61..f910e8e1f2c8fb 100644
--- a/llvm/unittests/MI/LiveIntervalTest.cpp
+++ b/llvm/unittests/MI/LiveIntervalTest.cpp
@@ -101,7 +101,9 @@ struct TestPassT : public TestPass {
bool runOnMachineFunction(MachineFunction &MF) override {
AnalysisType &A = getAnalysis<AnalysisType>();
T(MF, A);
- EXPECT_EQ(MF.verify(this, /* Banner */ nullptr, /* AbortOnError */ false),
+ EXPECT_EQ(MF.verify(this, /* Banner=*/nullptr,
+ /*OS=*/nullptr,
+ /* AbortOnError=*/false),
ShouldPass);
return true;
}
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