[llvm] 19f04e9 - [AArch64] Use MCRegister in more places. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 23 10:25:10 PDT 2024
Author: Craig Topper
Date: 2024-09-23T10:24:48-07:00
New Revision: 19f04e908667aade0efe2de9ae705baaf68c0ce2
URL: https://github.com/llvm/llvm-project/commit/19f04e908667aade0efe2de9ae705baaf68c0ce2
DIFF: https://github.com/llvm/llvm-project/commit/19f04e908667aade0efe2de9ae705baaf68c0ce2.diff
LOG: [AArch64] Use MCRegister in more places. NFC
Added:
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 4f6131fd835577..6a4b94a216832e 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -136,8 +136,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
assert(Predicated);
return ElementSize;
}
- unsigned getDstReg() const { return Dst; }
- unsigned getPgReg() const {
+ MCRegister getDstReg() const { return Dst; }
+ MCRegister getPgReg() const {
assert(Predicated);
return Pg;
}
@@ -146,8 +146,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool Active = false;
bool Predicated = false;
unsigned ElementSize;
- unsigned Dst;
- unsigned Pg;
+ MCRegister Dst;
+ MCRegister Pg;
} NextPrefix;
AArch64TargetStreamer &getTargetStreamer() {
@@ -5234,7 +5234,7 @@ bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
return false;
}
-static inline bool isMatchingOrAlias(unsigned ZReg, unsigned Reg) {
+static inline bool isMatchingOrAlias(MCRegister ZReg, MCRegister Reg) {
assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31));
return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) ||
(ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) ||
@@ -5322,7 +5322,7 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
if (IsWindowsArm64EC) {
for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
if (Inst.getOperand(i).isReg()) {
- unsigned Reg = Inst.getOperand(i).getReg();
+ MCRegister Reg = Inst.getOperand(i).getReg();
// At this point, vector registers are matched to their
// appropriately sized alias.
if ((Reg == AArch64::W13 || Reg == AArch64::X13) ||
@@ -5351,9 +5351,9 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::LDPWpre:
case AArch64::LDPXpost:
case AArch64::LDPXpre: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
- unsigned Rn = Inst.getOperand(3).getReg();
+ MCRegister Rt = Inst.getOperand(1).getReg();
+ MCRegister Rt2 = Inst.getOperand(2).getReg();
+ MCRegister Rn = Inst.getOperand(3).getReg();
if (RI->isSubRegisterEq(Rn, Rt))
return Error(Loc[0], "unpredictable LDP instruction, writeback base "
"is also a destination");
@@ -5376,8 +5376,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::LDPSWi:
case AArch64::LDPWi:
case AArch64::LDPXi: {
- unsigned Rt = Inst.getOperand(0).getReg();
- unsigned Rt2 = Inst.getOperand(1).getReg();
+ MCRegister Rt = Inst.getOperand(0).getReg();
+ MCRegister Rt2 = Inst.getOperand(1).getReg();
if (Rt == Rt2)
return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
break;
@@ -5389,8 +5389,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::LDPSpost:
case AArch64::LDPSpre:
case AArch64::LDPSWpost: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
+ MCRegister Rt = Inst.getOperand(1).getReg();
+ MCRegister Rt2 = Inst.getOperand(2).getReg();
if (Rt == Rt2)
return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
break;
@@ -5405,9 +5405,9 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::STPWpre:
case AArch64::STPXpost:
case AArch64::STPXpre: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
- unsigned Rn = Inst.getOperand(3).getReg();
+ MCRegister Rt = Inst.getOperand(1).getReg();
+ MCRegister Rt2 = Inst.getOperand(2).getReg();
+ MCRegister Rn = Inst.getOperand(3).getReg();
if (RI->isSubRegisterEq(Rn, Rt))
return Error(Loc[0], "unpredictable STP instruction, writeback base "
"is also a source");
@@ -5438,8 +5438,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::LDRSWpost:
case AArch64::LDRWpost:
case AArch64::LDRXpost: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rn = Inst.getOperand(2).getReg();
+ MCRegister Rt = Inst.getOperand(1).getReg();
+ MCRegister Rn = Inst.getOperand(2).getReg();
if (RI->isSubRegisterEq(Rn, Rt))
return Error(Loc[0], "unpredictable LDR instruction, writeback base "
"is also a source");
@@ -5457,8 +5457,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::STRHpre:
case AArch64::STRWpre:
case AArch64::STRXpre: {
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rn = Inst.getOperand(2).getReg();
+ MCRegister Rt = Inst.getOperand(1).getReg();
+ MCRegister Rn = Inst.getOperand(2).getReg();
if (RI->isSubRegisterEq(Rn, Rt))
return Error(Loc[0], "unpredictable STR instruction, writeback base "
"is also a source");
@@ -5472,9 +5472,9 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::STLXRH:
case AArch64::STLXRW:
case AArch64::STLXRX: {
- unsigned Rs = Inst.getOperand(0).getReg();
- unsigned Rt = Inst.getOperand(1).getReg();
- unsigned Rn = Inst.getOperand(2).getReg();
+ MCRegister Rs = Inst.getOperand(0).getReg();
+ MCRegister Rt = Inst.getOperand(1).getReg();
+ MCRegister Rn = Inst.getOperand(2).getReg();
if (RI->isSubRegisterEq(Rt, Rs) ||
(RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
return Error(Loc[0],
@@ -5485,10 +5485,10 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::STXPX:
case AArch64::STLXPW:
case AArch64::STLXPX: {
- unsigned Rs = Inst.getOperand(0).getReg();
- unsigned Rt1 = Inst.getOperand(1).getReg();
- unsigned Rt2 = Inst.getOperand(2).getReg();
- unsigned Rn = Inst.getOperand(3).getReg();
+ MCRegister Rs = Inst.getOperand(0).getReg();
+ MCRegister Rt1 = Inst.getOperand(1).getReg();
+ MCRegister Rt2 = Inst.getOperand(2).getReg();
+ MCRegister Rn = Inst.getOperand(3).getReg();
if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
(RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
return Error(Loc[0],
@@ -5497,8 +5497,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
}
case AArch64::LDRABwriteback:
case AArch64::LDRAAwriteback: {
- unsigned Xt = Inst.getOperand(0).getReg();
- unsigned Xn = Inst.getOperand(1).getReg();
+ MCRegister Xt = Inst.getOperand(0).getReg();
+ MCRegister Xn = Inst.getOperand(1).getReg();
if (Xt == Xn)
return Error(Loc[0],
"unpredictable LDRA instruction, writeback base"
@@ -5605,12 +5605,12 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::CPYETWN:
case AArch64::CPYETRN:
case AArch64::CPYETN: {
- unsigned Xd_wb = Inst.getOperand(0).getReg();
- unsigned Xs_wb = Inst.getOperand(1).getReg();
- unsigned Xn_wb = Inst.getOperand(2).getReg();
- unsigned Xd = Inst.getOperand(3).getReg();
- unsigned Xs = Inst.getOperand(4).getReg();
- unsigned Xn = Inst.getOperand(5).getReg();
+ MCRegister Xd_wb = Inst.getOperand(0).getReg();
+ MCRegister Xs_wb = Inst.getOperand(1).getReg();
+ MCRegister Xn_wb = Inst.getOperand(2).getReg();
+ MCRegister Xd = Inst.getOperand(3).getReg();
+ MCRegister Xs = Inst.getOperand(4).getReg();
+ MCRegister Xn = Inst.getOperand(5).getReg();
if (Xd_wb != Xd)
return Error(Loc[0],
"invalid CPY instruction, Xd_wb and Xd do not match");
@@ -5655,11 +5655,11 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::MOPSSETGET:
case AArch64::MOPSSETGEN:
case AArch64::MOPSSETGETN: {
- unsigned Xd_wb = Inst.getOperand(0).getReg();
- unsigned Xn_wb = Inst.getOperand(1).getReg();
- unsigned Xd = Inst.getOperand(2).getReg();
- unsigned Xn = Inst.getOperand(3).getReg();
- unsigned Xm = Inst.getOperand(4).getReg();
+ MCRegister Xd_wb = Inst.getOperand(0).getReg();
+ MCRegister Xn_wb = Inst.getOperand(1).getReg();
+ MCRegister Xd = Inst.getOperand(2).getReg();
+ MCRegister Xn = Inst.getOperand(3).getReg();
+ MCRegister Xm = Inst.getOperand(4).getReg();
if (Xd_wb != Xd)
return Error(Loc[0],
"invalid SET instruction, Xd_wb and Xd do not match");
@@ -6451,7 +6451,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// GPR64. Twiddle it here if necessary.
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
if (Op.isScalarReg()) {
- unsigned Reg = getXRegFromWReg(Op.getReg());
+ MCRegister Reg = getXRegFromWReg(Op.getReg());
Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
Op.getStartLoc(), Op.getEndLoc(),
getContext());
@@ -6467,7 +6467,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// GPR64. Twiddle it here if necessary.
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
if (Op.isScalarReg()) {
- unsigned Reg = getXRegFromWReg(Op.getReg());
+ MCRegister Reg = getXRegFromWReg(Op.getReg());
Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
Op.getStartLoc(),
Op.getEndLoc(), getContext());
@@ -6484,7 +6484,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// GPR32. Twiddle it here if necessary.
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
if (Op.isScalarReg()) {
- unsigned Reg = getWRegFromXReg(Op.getReg());
+ MCRegister Reg = getWRegFromXReg(Op.getReg());
Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
Op.getStartLoc(),
Op.getEndLoc(), getContext());
@@ -7907,7 +7907,7 @@ ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
return Error(E, "expected second odd register of a consecutive same-size "
"even/odd register pair");
- unsigned Pair = 0;
+ MCRegister Pair;
if (isXReg) {
Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
&AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]);
@@ -8047,7 +8047,7 @@ ParseStatus AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
MCContext &ctx = getContext();
const MCRegisterInfo *RI = ctx.getRegisterInfo();
- int X8Reg = RI->getMatchingSuperReg(
+ MCRegister X8Reg = RI->getMatchingSuperReg(
XReg, AArch64::x8sub_0,
&AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID]);
if (!X8Reg)
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index 924d64b66b2235..adc6c5bf4ed171 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -622,7 +622,7 @@ class DarwinAArch64AsmBackend : public AArch64AsmBackend {
return CU::UNWIND_ARM64_MODE_DWARF;
case MCCFIInstruction::OpDefCfa: {
// Defines a frame pointer.
- unsigned XReg =
+ MCRegister XReg =
getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true));
// Other CFA registers than FP are not supported by compact unwind.
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index c5de5b4de4aef3..7c9113f6bc2380 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -815,14 +815,14 @@ void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
O << '[' << MI->getOperand(OpNum++).getImm() << ']';
// Next the address: [xN]
- unsigned AddrReg = MI->getOperand(OpNum++).getReg();
+ MCRegister AddrReg = MI->getOperand(OpNum++).getReg();
O << ", [";
printRegName(O, AddrReg);
O << ']';
// Finally, there might be a post-indexed offset.
if (LdStDesc->NaturalOffset != 0) {
- unsigned Reg = MI->getOperand(OpNum++).getReg();
+ MCRegister Reg = MI->getOperand(OpNum++).getReg();
if (Reg != AArch64::XZR) {
O << ", ";
printRegName(O, Reg);
@@ -860,7 +860,7 @@ bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
if ((PRFOp & Mask) != Mask)
return false; // Rt != '11xxx', it's a PRFM instruction.
- unsigned Rm = MI->getOperand(2).getReg();
+ MCRegister Rm = MI->getOperand(2).getReg();
// "Rm" must be a 64-bit GPR for RPRFM.
if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
@@ -1143,8 +1143,7 @@ void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
- unsigned Reg = Op.getReg();
- printRegName(O, Reg);
+ printRegName(O, Op.getReg());
} else if (Op.isImm()) {
printImm(MI, OpNo, STI, O);
} else {
@@ -1184,7 +1183,7 @@ void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
unsigned Imm, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
if (Reg == AArch64::XZR)
markup(O, Markup::Immediate) << "#" << Imm;
else
@@ -1198,8 +1197,7 @@ void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
assert(Op.isReg() && "Non-register vreg operand!");
- unsigned Reg = Op.getReg();
- printRegName(O, Reg, AArch64::vreg);
+ printRegName(O, Op.getReg(), AArch64::vreg);
}
void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
@@ -1280,8 +1278,8 @@ void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
// UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
// all.
if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
- unsigned Dest = MI->getOperand(0).getReg();
- unsigned Src1 = MI->getOperand(1).getReg();
+ MCRegister Dest = MI->getOperand(0).getReg();
+ MCRegister Src1 = MI->getOperand(1).getReg();
if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
ExtType == AArch64_AM::UXTX) ||
((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
@@ -1347,7 +1345,7 @@ void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
if (Reg < AArch64::PN0 || Reg > AArch64::PN15)
llvm_unreachable("Unsupported predicate-as-counter register");
O << "pn" << Reg - AArch64::PN0;
@@ -1504,9 +1502,9 @@ void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
markup(O, Markup::Immediate) << format("#%.8f", FPImm);
}
-static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
+static MCRegister getNextVectorRegister(MCRegister Reg, unsigned Stride = 1) {
while (Stride--) {
- switch (Reg) {
+ switch (Reg.id()) {
default:
llvm_unreachable("Vector register expected!");
case AArch64::Q0: Reg = AArch64::Q1; break;
@@ -1608,13 +1606,13 @@ void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
raw_ostream &O) {
static_assert(size == 64 || size == 32,
"Template parameter must be either 32 or 64");
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
- unsigned Even = MRI.getSubReg(Reg, Sube);
- unsigned Odd = MRI.getSubReg(Reg, Subo);
+ MCRegister Even = MRI.getSubReg(Reg, Sube);
+ MCRegister Odd = MRI.getSubReg(Reg, Subo);
printRegName(O, Even);
O << ", ";
printRegName(O, Odd);
@@ -1649,7 +1647,7 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O,
StringRef LayoutSuffix) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
O << "{ ";
@@ -1679,13 +1677,13 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
Stride = 4;
// Now forget about the list and find out what the first register is.
- if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
+ if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
Reg = FirstReg;
- else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
+ else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
Reg = FirstReg;
- else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
+ else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
Reg = FirstReg;
- else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
+ else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::psub0))
Reg = FirstReg;
// If it's a D-reg, we need to promote it to the equivalent Q-reg before
@@ -2008,7 +2006,7 @@ void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
default: llvm_unreachable("Invalid kind specifier.");
}
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
printRegName(O, Reg);
if (suffix != 0)
O << '.' << suffix;
@@ -2090,7 +2088,7 @@ void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
default:
llvm_unreachable("Unsupported width");
}
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
printRegName(O, Reg - AArch64::Z0 + Base);
}
@@ -2108,21 +2106,21 @@ void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
printRegName(O, getWRegFromXReg(Reg));
}
void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
}
void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- unsigned Reg = MI->getOperand(OpNum).getReg();
+ MCRegister Reg = MI->getOperand(OpNum).getReg();
assert(Reg == AArch64::XZR &&
"MC representation of SyspXzrPair should be XZR");
O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index f821bb527aedb8..9faecccb1bd104 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -27,8 +27,8 @@
namespace llvm {
-inline static unsigned getWRegFromXReg(unsigned Reg) {
- switch (Reg) {
+inline static MCRegister getWRegFromXReg(MCRegister Reg) {
+ switch (Reg.id()) {
case AArch64::X0: return AArch64::W0;
case AArch64::X1: return AArch64::W1;
case AArch64::X2: return AArch64::W2;
@@ -67,8 +67,8 @@ inline static unsigned getWRegFromXReg(unsigned Reg) {
return Reg;
}
-inline static unsigned getXRegFromWReg(unsigned Reg) {
- switch (Reg) {
+inline static MCRegister getXRegFromWReg(MCRegister Reg) {
+ switch (Reg.id()) {
case AArch64::W0: return AArch64::X0;
case AArch64::W1: return AArch64::X1;
case AArch64::W2: return AArch64::X2;
@@ -107,8 +107,8 @@ inline static unsigned getXRegFromWReg(unsigned Reg) {
return Reg;
}
-inline static unsigned getXRegFromXRegTuple(unsigned RegTuple) {
- switch (RegTuple) {
+inline static MCRegister getXRegFromXRegTuple(MCRegister RegTuple) {
+ switch (RegTuple.id()) {
case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
@@ -126,8 +126,8 @@ inline static unsigned getXRegFromXRegTuple(unsigned RegTuple) {
return RegTuple;
}
-static inline unsigned getBRegFromDReg(unsigned Reg) {
- switch (Reg) {
+static inline MCRegister getBRegFromDReg(MCRegister Reg) {
+ switch (Reg.id()) {
case AArch64::D0: return AArch64::B0;
case AArch64::D1: return AArch64::B1;
case AArch64::D2: return AArch64::B2;
@@ -165,9 +165,8 @@ static inline unsigned getBRegFromDReg(unsigned Reg) {
return Reg;
}
-
-static inline unsigned getDRegFromBReg(unsigned Reg) {
- switch (Reg) {
+static inline MCRegister getDRegFromBReg(MCRegister Reg) {
+ switch (Reg.id()) {
case AArch64::B0: return AArch64::D0;
case AArch64::B1: return AArch64::D1;
case AArch64::B2: return AArch64::D2;
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