[llvm] MTM: improve operand latency when missing sched info (PR #101389)

[Ramkumar Ramachandra via llvm-commits]

artagnon wrote:

> Is this only useful for incomplete targets?

It is useful when the CPU doesn't have a scheduler descriptor checked into the tree. This happens in the real-world on my X86 box, for instance.

https://github.com/llvm/llvm-project/pull/101389