[llvm] [X86, SimplifyCFG] Support hoisting load/store with conditional faulting (Part II) (PR #108812)

Phoebe Wang via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 23 02:50:22 PDT 2024


================
@@ -1663,18 +1663,29 @@ static bool areIdenticalUpToCommutativity(const Instruction *I1,
 static void hoistConditionalLoadsStores(
     BranchInst *BI,
     SmallVectorImpl<Instruction *> &SpeculatedConditionalLoadsStores,
-    bool Invert) {
+    std::optional<bool> Invert) {
   auto &Context = BI->getParent()->getContext();
   auto *VCondTy = FixedVectorType::get(Type::getInt1Ty(Context), 1);
   auto *Cond = BI->getOperand(0);
   // Construct the condition if needed.
   BasicBlock *BB = BI->getParent();
-  IRBuilder<> Builder(SpeculatedConditionalLoadsStores.back());
-  Value *Mask = Builder.CreateBitCast(
-      Invert ? Builder.CreateXor(Cond, ConstantInt::getTrue(Context)) : Cond,
-      VCondTy);
+  IRBuilder<> Builder(Invert ? SpeculatedConditionalLoadsStores.back() : BI);
----------------
phoebewang wrote:

No, cannot. Because in the triangle case, the `SpeculatedConditionalLoadsStores` was pushed in reverse order, we must get the insertion point one by one for it, otherwise, we will get something like
```
define void @basic(i1 %cond, ptr %b, ptr %p, ptr %q) #0 {
entry:
  %0 = bitcast i1 %cond to <1 x i1>
  %1 = bitcast i64 %5 to <1 x i64>
  call void @llvm.masked.store.v1i64.p0(<1 x i64> %1, ptr %q, i32 8, <1 x i1> %0)
  %2 = bitcast i32 %7 to <1 x i32>
  call void @llvm.masked.store.v1i32.p0(<1 x i32> %2, ptr %p, i32 4, <1 x i1> %0)
  %3 = bitcast i16 %9 to <1 x i16>
  call void @llvm.masked.store.v1i16.p0(<1 x i16> %3, ptr %b, i32 2, <1 x i1> %0)
  %4 = call <1 x i64> @llvm.masked.load.v1i64.p0(ptr %b, i32 8, <1 x i1> %0, <1 x i64> poison)
  %5 = bitcast <1 x i64> %4 to i64
  %6 = call <1 x i32> @llvm.masked.load.v1i32.p0(ptr %q, i32 4, <1 x i1> %0, <1 x i32> poison)
  %7 = bitcast <1 x i32> %6 to i32
  %8 = call <1 x i16> @llvm.masked.load.v1i16.p0(ptr %p, i32 2, <1 x i1> %0, <1 x i16> poison)
  %9 = bitcast <1 x i16> %8 to i16
  ret void
}
```

https://github.com/llvm/llvm-project/pull/108812


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