[clang] [llvm] [Clang][LLVM][AArch64] Add intrinsic for MOVT SME2 instruction (PR #97602)

[via llvm-commits]

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@@ -2899,6 +2899,15 @@ let TargetPrefix = "aarch64" in {
           [llvm_i32_ty],
           [IntrNoMem, IntrHasSideEffects]>;
 
+  def int_aarch64_sme_write_lane_zt
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CarolineConcatto wrote:

So ZT0 is a register and not a memory.
 I believe the correct way to model this is with IntraHasSideEffects and not correct to model this as writing in memory.

https://github.com/llvm/llvm-project/pull/97602