[llvm] 84b1489 - [ARM] Update VBIC tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 23 00:34:19 PDT 2024
Author: David Green
Date: 2024-09-23T08:34:15+01:00
New Revision: 84b1489c8f8d4fb3c541167301c29ee4dad1af78
URL: https://github.com/llvm/llvm-project/commit/84b1489c8f8d4fb3c541167301c29ee4dad1af78
DIFF: https://github.com/llvm/llvm-project/commit/84b1489c8f8d4fb3c541167301c29ee4dad1af78.diff
LOG: [ARM] Update VBIC tests. NFC
Added:
Modified:
llvm/test/CodeGen/ARM/vbsl.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/vbsl.ll b/llvm/test/CodeGen/ARM/vbsl.ll
index 735fa5182fe751..8564a48fbc3dbc 100644
--- a/llvm/test/CodeGen/ARM/vbsl.ll
+++ b/llvm/test/CodeGen/ARM/vbsl.ll
@@ -1,17 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-; rdar://12471808
+; RUN: llc -mtriple=armv7-eabihf -mattr=+neon %s -o - | FileCheck %s
define <8 x i8> @v_bsli8(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bsli8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
; CHECK-NEXT: vldr d16, [r2]
+; CHECK-NEXT: vorr d0, d18, d18
; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d17, d16
+; CHECK-NEXT: bx lr
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = load <8 x i8>, ptr %B
%tmp3 = load <8 x i8>, ptr %C
@@ -27,10 +25,10 @@ define <4 x i16> @v_bsli16(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
; CHECK-NEXT: vldr d16, [r2]
+; CHECK-NEXT: vorr d0, d18, d18
; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d17, d16
+; CHECK-NEXT: bx lr
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = load <4 x i16>, ptr %B
%tmp3 = load <4 x i16>, ptr %C
@@ -46,10 +44,10 @@ define <2 x i32> @v_bsli32(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
; CHECK-NEXT: vldr d16, [r2]
+; CHECK-NEXT: vorr d0, d18, d18
; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d17, d16
+; CHECK-NEXT: bx lr
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = load <2 x i32>, ptr %B
%tmp3 = load <2 x i32>, ptr %C
@@ -65,10 +63,10 @@ define <1 x i64> @v_bsli64(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d18, [r0]
; CHECK-NEXT: vldr d16, [r2]
+; CHECK-NEXT: vorr d0, d18, d18
; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d17, d16
+; CHECK-NEXT: bx lr
%tmp1 = load <1 x i64>, ptr %A
%tmp2 = load <1 x i64>, ptr %B
%tmp3 = load <1 x i64>, ptr %C
@@ -83,12 +81,11 @@ define <16 x i8> @v_bslQi8(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: vorr q0, q10, q10
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vbit q8, q9, q10
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q9, q8
+; CHECK-NEXT: bx lr
%tmp1 = load <16 x i8>, ptr %A
%tmp2 = load <16 x i8>, ptr %B
%tmp3 = load <16 x i8>, ptr %C
@@ -103,12 +100,11 @@ define <8 x i16> @v_bslQi16(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: vorr q0, q10, q10
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vbit q8, q9, q10
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q9, q8
+; CHECK-NEXT: bx lr
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = load <8 x i16>, ptr %B
%tmp3 = load <8 x i16>, ptr %C
@@ -123,12 +119,11 @@ define <4 x i32> @v_bslQi32(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: vorr q0, q10, q10
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vbit q8, q9, q10
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q9, q8
+; CHECK-NEXT: bx lr
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = load <4 x i32>, ptr %B
%tmp3 = load <4 x i32>, ptr %C
@@ -143,12 +138,11 @@ define <2 x i64> @v_bslQi64(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: v_bslQi64:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: vorr q0, q10, q10
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vbit q8, q9, q10
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q9, q8
+; CHECK-NEXT: bx lr
%tmp1 = load <2 x i64>, ptr %A
%tmp2 = load <2 x i64>, ptr %B
%tmp3 = load <2 x i64>, ptr %C
@@ -162,12 +156,8 @@ define <2 x i64> @v_bslQi64(ptr %A, ptr %B, ptr %C) nounwind {
define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: f1:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d1, d2
+; CHECK-NEXT: bx lr
%vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
ret <8 x i8> %vbsl.i
}
@@ -175,12 +165,8 @@ define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone opt
define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: f2:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d1, d2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
ret <4 x i16> %vbsl3.i
}
@@ -188,12 +174,8 @@ define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone
define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: f3:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d1, d2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
ret <2 x i32> %vbsl3.i
}
@@ -201,12 +183,8 @@ define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone
define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: f4:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d1, d2
+; CHECK-NEXT: bx lr
%vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
ret <2 x float> %vbsl4.i
}
@@ -214,16 +192,8 @@ define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: g1:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d19, r2, r3
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT: vbit q8, q10, q9
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q1, q2
+; CHECK-NEXT: bx lr
%vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
ret <16 x i8> %vbsl.i
}
@@ -231,16 +201,8 @@ define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone
define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: g2:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d19, r2, r3
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT: vbit q8, q10, q9
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q1, q2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
ret <8 x i16> %vbsl3.i
}
@@ -248,16 +210,8 @@ define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone
define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: g3:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d19, r2, r3
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT: vbit q8, q10, q9
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q1, q2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
ret <4 x i32> %vbsl3.i
}
@@ -265,16 +219,8 @@ define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone
define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: g4:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d19, r2, r3
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT: vbit q8, q10, q9
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q1, q2
+; CHECK-NEXT: bx lr
%vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
ret <4 x float> %vbsl4.i
}
@@ -282,12 +228,8 @@ define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: test_vbsl_s64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d1, d2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
ret <1 x i64> %vbsl3.i
}
@@ -295,12 +237,8 @@ define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwi
define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: test_vbsl_u64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: vbit d16, d17, d18
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl d0, d1, d2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
ret <1 x i64> %vbsl3.i
}
@@ -308,16 +246,8 @@ define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwi
define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: test_vbslq_s64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d19, r2, r3
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT: vbit q8, q10, q9
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q1, q2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
ret <2 x i64> %vbsl3.i
}
@@ -325,16 +255,8 @@ define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounw
define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
; CHECK-LABEL: test_vbslq_u64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d19, r2, r3
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d18, r0, r1
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
-; CHECK-NEXT: vbit q8, q10, q9
-; CHECK-NEXT: vmov r0, r1, d16
-; CHECK-NEXT: vmov r2, r3, d17
-; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: vbsl q0, q1, q2
+; CHECK-NEXT: bx lr
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
ret <2 x i64> %vbsl3.i
}
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