[llvm] [X86][IPRA] Add getIPRACSRegs since rbp is risked to be optimized out. (PR #109597)
Freddy Ye via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 22 19:16:13 PDT 2024
https://github.com/FreddyLeaf created https://github.com/llvm/llvm-project/pull/109597
This patch is a workaround to fix the correctness of IPRA on X86.
>From 8ada603aee6d62093ce0e1d431d8ddf654150b3c Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Tue, 3 Sep 2024 17:07:19 +0800
Subject: [PATCH] [X86][IPRA] Add getIPRACSRegs since rbp is risked to be
optimized out.
This patch is a workaround to fix the correctness of IPRA on X86.
---
.../include/llvm/CodeGen/TargetRegisterInfo.h | 4 ++
llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | 6 ++-
llvm/lib/Target/X86/X86CallingConv.td | 3 ++
llvm/lib/Target/X86/X86RegisterInfo.cpp | 5 +++
llvm/lib/Target/X86/X86RegisterInfo.h | 3 ++
llvm/test/CodeGen/X86/ipra-local-linkage-2.ll | 37 +++++++++++++++++++
6 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/ipra-local-linkage-2.ll
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 1a2f31e199336a..0f6484fddfe61f 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -489,6 +489,10 @@ class TargetRegisterInfo : public MCRegisterInfo {
virtual const MCPhysReg*
getCalleeSavedRegs(const MachineFunction *MF) const = 0;
+ /// Return a null-terminated list of all of the callee-saved registers on
+ /// this target when IPRA is on. Normally, this list should be null.
+ virtual const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const = 0;
+
/// Return a mask of call-preserved registers for the given calling convention
/// on the current function. The mask should include all call-preserved
/// aliases. This is used by the register allocator to determine which
diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
index 7d054cb7c7c71f..364cc933731dec 100644
--- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
+++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
@@ -107,8 +107,12 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
// are preferred over callee saved registers.
if (MF.getTarget().Options.EnableIPRA &&
isSafeForNoCSROpt(MF.getFunction()) &&
- isProfitableForNoCSROpt(MF.getFunction()))
+ isProfitableForNoCSROpt(MF.getFunction())) {
+ const MCPhysReg *IPRACSRegs = TRI.getIPRACSRegs(&MF);
+ for (unsigned i = 0; IPRACSRegs[i]; ++i)
+ SavedRegs.set(IPRACSRegs[i]);
return;
+ }
// Get the callee saved register list...
const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
diff --git a/llvm/lib/Target/X86/X86CallingConv.td b/llvm/lib/Target/X86/X86CallingConv.td
index 307aeb2ea4c6fd..472823a6d036ba 100644
--- a/llvm/lib/Target/X86/X86CallingConv.td
+++ b/llvm/lib/Target/X86/X86CallingConv.td
@@ -1104,6 +1104,9 @@ def CC_X86 : CallingConv<[
def CSR_NoRegs : CalleeSavedRegs<(add)>;
+def CSR_IPRA_32 : CalleeSavedRegs<(add EBP)>;
+def CSR_IPRA_64 : CalleeSavedRegs<(add RBP)>;
+
def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 1d8808f4e2b7d0..302d50581e1e6b 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -410,6 +410,11 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
}
+const MCPhysReg *
+X86RegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
+ return Is64Bit ? CSR_IPRA_64_SaveList : CSR_IPRA_32_SaveList;
+}
+
const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
const MachineFunction *MF) const {
assert(MF && "Invalid MachineFunction pointer.");
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h
index 2f73698a4b94d3..68ee372f27b14d 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.h
+++ b/llvm/lib/Target/X86/X86RegisterInfo.h
@@ -99,6 +99,9 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
/// callee-save registers on this target.
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction* MF) const override;
+ /// getIPRACSRegs - This API can be removed when rbp is safe to optimized out
+ /// when IPRA is on.
+ const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;
const MCPhysReg *
getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
diff --git a/llvm/test/CodeGen/X86/ipra-local-linkage-2.ll b/llvm/test/CodeGen/X86/ipra-local-linkage-2.ll
new file mode 100644
index 00000000000000..f337dfc989d81a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/ipra-local-linkage-2.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -enable-ipra < %s | FileCheck %s
+
+; This test is to ensure rbp is correctly saved/restored before/after the
+; inline asm call in foo()
+
+target triple = "x86_64--"
+
+define internal void @foo() norecurse nounwind {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: #APP
+; CHECK-NEXT: xorl %ebp, %ebp
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ call void asm sideeffect "xor %ebp, %ebp", "~{ebp}"()
+ ret void
+}
+
+define void @bar(i32 %X) "frame-pointer"="all" nounwind {
+; CHECK-LABEL: bar:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: subq $16, %rsp
+; CHECK-NEXT: callq foo
+; CHECK-NEXT: movl $5, -4(%rbp)
+; CHECK-NEXT: addq $16, %rsp
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: retq
+ call void @foo()
+ %addr = alloca i32, align 4
+ store i32 5, ptr %addr, align 4
+ ret void
+}
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