[llvm] b47af5d - [MC] Replace some comparisons of MCRegister and literal 0. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 21 23:29:54 PDT 2024
Author: Craig Topper
Date: 2024-09-21T23:25:24-07:00
New Revision: b47af5d1480e83304017a846488aaeac679ee855
URL: https://github.com/llvm/llvm-project/commit/b47af5d1480e83304017a846488aaeac679ee855
DIFF: https://github.com/llvm/llvm-project/commit/b47af5d1480e83304017a846488aaeac679ee855.diff
LOG: [MC] Replace some comparisons of MCRegister and literal 0. NFC
We can convert the MCRegister to bool instead. I think this should
allows us to remove MCRegister::operator==(int). All other comparisons
in tree are unsigned.
Added:
Modified:
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/lib/Target/X86/AsmParser/X86Operand.h
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 2d7f924b44ac81..75fb90477f8854 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1483,8 +1483,8 @@ class ARMOperand : public MCParsedAsmOperand {
if (!isGPRMem())
return false;
// No offset of any kind.
- return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
- (alignOK || Memory.Alignment == Alignment);
+ return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
+ (alignOK || Memory.Alignment == Alignment);
}
bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
if (!isGPRMem())
@@ -1495,8 +1495,8 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// No offset of any kind.
- return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
- (alignOK || Memory.Alignment == Alignment);
+ return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
+ (alignOK || Memory.Alignment == Alignment);
}
bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
if (!isGPRMem())
@@ -1507,8 +1507,8 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// No offset of any kind.
- return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
- (alignOK || Memory.Alignment == Alignment);
+ return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
+ (alignOK || Memory.Alignment == Alignment);
}
bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
if (!isGPRMem())
@@ -1519,11 +1519,11 @@ class ARMOperand : public MCParsedAsmOperand {
return false;
// No offset of any kind.
- return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
- (alignOK || Memory.Alignment == Alignment);
+ return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
+ (alignOK || Memory.Alignment == Alignment);
}
bool isMemPCRelImm12() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Base register must be PC.
if (Memory.BaseRegNum != ARM::PC)
@@ -1754,7 +1754,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemThumbRIs4() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
+ if (!isGPRMem() || Memory.OffsetRegNum ||
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
return false;
// Immediate offset, multiple of 4 in range [0, 124].
@@ -1767,7 +1767,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemThumbRIs2() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
+ if (!isGPRMem() || Memory.OffsetRegNum ||
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
return false;
// Immediate offset, multiple of 4 in range [0, 62].
@@ -1780,7 +1780,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemThumbRIs1() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
+ if (!isGPRMem() || Memory.OffsetRegNum ||
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
return false;
// Immediate offset in range [0, 31].
@@ -1793,8 +1793,8 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemThumbSPI() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
- Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.BaseRegNum != ARM::SP ||
+ Memory.Alignment != 0)
return false;
// Immediate offset, multiple of 4 in range [0, 1020].
if (!Memory.OffsetImm) return true;
@@ -1811,7 +1811,7 @@ class ARMOperand : public MCParsedAsmOperand {
// and we reject it.
if (isImm() && !isa<MCConstantExpr>(getImm()))
return true;
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Immediate offset a multiple of 4 in range [-1020, 1020].
if (!Memory.OffsetImm) return true;
@@ -1830,7 +1830,7 @@ class ARMOperand : public MCParsedAsmOperand {
// and we reject it.
if (isImm() && !isa<MCConstantExpr>(getImm()))
return true;
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0 ||
!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
Memory.BaseRegNum))
return false;
@@ -1845,7 +1845,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemImm0_1020s4Offset() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Immediate offset a multiple of 4 in range [0, 1020].
if (!Memory.OffsetImm) return true;
@@ -1857,7 +1857,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemImm8Offset() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Base reg of PC isn't allowed for these encodings.
if (Memory.BaseRegNum == ARM::PC) return false;
@@ -1873,7 +1873,7 @@ class ARMOperand : public MCParsedAsmOperand {
template<unsigned Bits, unsigned RegClassID>
bool isMemImm7ShiftedOffset() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0 ||
!ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
return false;
@@ -1924,7 +1924,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
template <int shift> bool isMemRegQOffset() const {
- if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isMVEMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
@@ -1952,7 +1952,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemPosImm8Offset() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Immediate offset in range [0, 255].
if (!Memory.OffsetImm) return true;
@@ -1964,7 +1964,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemNegImm8Offset() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Base reg of PC isn't allowed for these encodings.
if (Memory.BaseRegNum == ARM::PC) return false;
@@ -1979,7 +1979,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isMemUImm12Offset() const {
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Immediate offset in range [0, 4095].
if (!Memory.OffsetImm) return true;
@@ -1998,7 +1998,7 @@ class ARMOperand : public MCParsedAsmOperand {
if (isImm() && !isa<MCConstantExpr>(getImm()))
return true;
- if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
+ if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
return false;
// Immediate offset in range [-4095, 4095].
if (!Memory.OffsetImm) return true;
@@ -8982,8 +8982,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
}
// Alias for alternate form of 'ADR Rd, #imm' instruction.
case ARM::ADDri: {
- if (Inst.getOperand(1).getReg() != ARM::PC ||
- Inst.getOperand(5).getReg() != 0 ||
+ if (Inst.getOperand(1).getReg() != ARM::PC || Inst.getOperand(5).getReg() ||
!(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
return false;
MCInst TmpInst;
@@ -10703,7 +10702,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
case ARM::t2ADDspImm:
case ARM::t2SUBspImm: {
// Prefer T1 encoding if possible
- if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier)
+ if (Inst.getOperand(5).getReg() || HasWideQualifier)
break;
unsigned V = Inst.getOperand(2).getImm();
if (V & 3 || V > ((1 << 7) - 1) << 2)
@@ -10732,9 +10731,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
Transform = true;
Swap = true;
}
- if (!Transform ||
- Inst.getOperand(5).getReg() != 0 ||
- HasWideQualifier)
+ if (!Transform || Inst.getOperand(5).getReg() || HasWideQualifier)
break;
MCInst TmpInst;
TmpInst.setOpcode(ARM::tADDhirr);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index 8a7339fd936b91..5636cc6287ac46 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -767,7 +767,7 @@ void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
- if (MO.getReg() == 0)
+ if (!MO.getReg())
O << "!";
else {
O << ", ";
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 9600293d3da71d..5e29a92f0bacd6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1356,7 +1356,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
// the register from VR to VRM2/VRM4/VRM8 if necessary.
if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
- if (Op.Reg.RegNum == 0)
+ if (!Op.Reg.RegNum)
return Match_InvalidOperand;
return Match_Success;
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index fc44f0b00a757c..ae30d4dfc70f53 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1399,14 +1399,14 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
RegNo = MatchRegisterName(RegName);
// If the match failed, try the register name as lowercase.
- if (RegNo == 0)
+ if (!RegNo)
RegNo = MatchRegisterName(RegName.lower());
// The "flags" and "mxcsr" registers cannot be referenced directly.
// Treat it as an identifier instead.
if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
(RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
- RegNo = 0;
+ RegNo = MCRegister();
if (!is64BitMode()) {
// FIXME: This should be done using Requires<Not64BitMode> and
@@ -1427,7 +1427,7 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
// If this is "db[0-15]", match it as an alias
// for dr[0-15].
- if (RegNo == 0 && RegName.starts_with("db")) {
+ if (!RegNo && RegName.starts_with("db")) {
if (RegName.size() == 3) {
switch (RegName[2]) {
case '0':
@@ -1485,7 +1485,7 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
}
}
- if (RegNo == 0) {
+ if (!RegNo) {
if (isParsingIntelSyntax())
return true;
return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc));
@@ -1497,7 +1497,7 @@ bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc, bool RestoreOnFailure) {
MCAsmParser &Parser = getParser();
MCAsmLexer &Lexer = getLexer();
- RegNo = 0;
+ RegNo = MCRegister();
SmallVector<AsmToken, 5> Tokens;
auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
@@ -1579,7 +1579,7 @@ bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
EndLoc = Parser.getTok().getEndLoc();
- if (RegNo == 0) {
+ if (!RegNo) {
OnFailure();
if (isParsingIntelSyntax()) return true;
return Error(StartLoc, "invalid register name",
@@ -3030,7 +3030,7 @@ bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
// base-index-scale-expr.
if (!parseOptionalToken(AsmToken::LParen)) {
- if (SegReg == 0)
+ if (!SegReg)
Operands.push_back(
X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
else
@@ -3119,7 +3119,7 @@ bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
// This is to support otherwise illegal operand (%dx) found in various
// unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
// be supported. Mark such DX variants separately fix only in special cases.
- if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
+ if (BaseReg == X86::DX && !IndexReg && Scale == 1 && !SegReg &&
isa<MCConstantExpr>(Disp) &&
cast<MCConstantExpr>(Disp)->getValue() == 0) {
Operands.push_back(X86Operand::CreateDXReg(BaseLoc, BaseLoc));
@@ -4920,14 +4920,14 @@ bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
// The SEH register number is the same as the encoding register number. Map
// from the encoding back to the LLVM register number.
- RegNo = 0;
+ RegNo = MCRegister();
for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
if (MRI->getEncodingValue(Reg) == EncodedReg) {
RegNo = Reg;
break;
}
}
- if (RegNo == 0) {
+ if (!RegNo) {
return Error(startLoc,
"incorrect register number for use with this directive");
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h
index 000278538e398b..03c333b90108e2 100644
--- a/llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -451,10 +451,11 @@ struct X86Operand final : public MCParsedAsmOperand {
bool isDstIdx() const {
return !getMemIndexReg() && getMemScale() == 1 &&
- (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
- (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
- getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
- cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
+ (!getMemSegReg() || getMemSegReg() == X86::ES) &&
+ (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
+ getMemBaseReg() == X86::DI) &&
+ isa<MCConstantExpr>(getMemDisp()) &&
+ cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
}
bool isDstIdx8() const {
return isMem8() && isDstIdx();
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index 87b46a3f55e771..1d08853faf582e 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -330,7 +330,7 @@ uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
}
}
- if (SegmentReg != 0)
+ if (SegmentReg)
return X86::getSegmentOverridePrefixForReg(SegmentReg);
if (STI.hasFeature(X86::Is64Bit))
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index ad7fdd7f637732..ba503756cf41a6 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -377,9 +377,9 @@ bool X86::optimizeMOV(MCInst &MI, bool In64BitMode) {
if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
Absolute = false;
}
- if (Absolute && (MI.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
+ if (Absolute && (MI.getOperand(AddrBase + X86::AddrBaseReg).getReg() ||
MI.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
- MI.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
+ MI.getOperand(AddrBase + X86::AddrIndexReg).getReg()))
return false;
// If so, rewrite the instruction.
MCOperand Saved = MI.getOperand(AddrOp);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 1bfb080ff50723..71d42863fd5857 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -621,8 +621,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
assert(STI.hasFeature(X86::Is64Bit) &&
"Rip-relative addressing requires 64-bit mode");
- assert(IndexReg.getReg() == 0 && !ForceSIB &&
- "Invalid rip-relative address");
+ assert(!IndexReg.getReg() && !ForceSIB && "Invalid rip-relative address");
emitByte(modRMByte(0, RegOpcodeField, 5), CB);
unsigned Opcode = MI.getOpcode();
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