[llvm] 58e0577 - [LV] Move test requiring AArch64 to target subdir.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 21 04:55:09 PDT 2024
Author: Florian Hahn
Date: 2024-09-21T12:54:59+01:00
New Revision: 58e05779b483bb3d9f734bd09f5cb2241431a0b7
URL: https://github.com/llvm/llvm-project/commit/58e05779b483bb3d9f734bd09f5cb2241431a0b7
DIFF: https://github.com/llvm/llvm-project/commit/58e05779b483bb3d9f734bd09f5cb2241431a0b7.diff
LOG: [LV] Move test requiring AArch64 to target subdir.
The test added in bd8fe9972e3f depends on the AArch64. Move it.
Added:
llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll
Modified:
Removed:
llvm/test/Transforms/LoopVectorize/invariant-replicate-region.ll
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll
new file mode 100644
index 00000000000000..e1472b7249ee64
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx14.0.0"
+
+; Test for https://github.com/llvm/llvm-project/issues/109510.
+define i32 @test_invariant_replicate_region(i32 %x, i1 %c) {
+; CHECK-LABEL: define i32 @test_invariant_replicate_region(
+; CHECK-SAME: i32 [[X:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_UREM_CONTINUE6:.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 0
+; CHECK-NEXT: br i1 [[TMP0]], label %[[PRED_UREM_IF:.*]], label %[[PRED_UREM_CONTINUE:.*]]
+; CHECK: [[PRED_UREM_IF]]:
+; CHECK-NEXT: [[TMP1:%.*]] = urem i32 10, [[X]]
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE]]
+; CHECK: [[PRED_UREM_CONTINUE]]:
+; CHECK-NEXT: [[TMP3:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP2]], %[[PRED_UREM_IF]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 1
+; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_UREM_IF1:.*]], label %[[PRED_UREM_CONTINUE2:.*]]
+; CHECK: [[PRED_UREM_IF1]]:
+; CHECK-NEXT: [[TMP5:%.*]] = urem i32 10, [[X]]
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP5]], i32 1
+; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE2]]
+; CHECK: [[PRED_UREM_CONTINUE2]]:
+; CHECK-NEXT: [[TMP7:%.*]] = phi <4 x i32> [ [[TMP3]], %[[PRED_UREM_CONTINUE]] ], [ [[TMP6]], %[[PRED_UREM_IF1]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 2
+; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_UREM_IF3:.*]], label %[[PRED_UREM_CONTINUE4:.*]]
+; CHECK: [[PRED_UREM_IF3]]:
+; CHECK-NEXT: [[TMP9:%.*]] = urem i32 10, [[X]]
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP9]], i32 2
+; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE4]]
+; CHECK: [[PRED_UREM_CONTINUE4]]:
+; CHECK-NEXT: [[TMP11:%.*]] = phi <4 x i32> [ [[TMP7]], %[[PRED_UREM_CONTINUE2]] ], [ [[TMP10]], %[[PRED_UREM_IF3]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 3
+; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_UREM_IF5:.*]], label %[[PRED_UREM_CONTINUE6]]
+; CHECK: [[PRED_UREM_IF5]]:
+; CHECK-NEXT: [[TMP13:%.*]] = urem i32 10, [[X]]
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP13]], i32 3
+; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE6]]
+; CHECK: [[PRED_UREM_CONTINUE6]]:
+; CHECK-NEXT: [[TMP15:%.*]] = phi <4 x i32> [ [[TMP11]], %[[PRED_UREM_CONTINUE4]] ], [ [[TMP14]], %[[PRED_UREM_IF5]] ]
+; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i32> [[TMP15]], <4 x i32> zeroinitializer
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
+; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3
+; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 100, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
+; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
+; CHECK: [[THEN]]:
+; CHECK-NEXT: [[REM_1:%.*]] = urem i32 10, [[X]]
+; CHECK-NEXT: br label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[RES:%.*]] = phi i32 [ 0, %[[LOOP_HEADER]] ], [ [[REM_1]], %[[THEN]] ]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], 99
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i32 [ [[RES]], %[[LOOP_LATCH]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i32 [[RES_LCSSA]]
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ br i1 %c, label %then, label %loop.latch
+
+then:
+ %rem.1 = urem i32 10, %x
+ br label %loop.latch
+
+loop.latch:
+ %res = phi i32 [ 0, %loop.header ], [ %rem.1, %then ]
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv, 99
+ br i1 %ec, label %exit, label %loop.header
+
+exit:
+ ret i32 %res
+}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/invariant-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/invariant-replicate-region.ll
deleted file mode 100644
index 34980aa2c378a6..00000000000000
--- a/llvm/test/Transforms/LoopVectorize/invariant-replicate-region.ll
+++ /dev/null
@@ -1,27 +0,0 @@
-; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
-
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
-target triple = "arm64-apple-macosx14.0.0"
-
-; Test for https://github.com/llvm/llvm-project/issues/109510.
-define i32 @test_invariant_replicate_region(i32 %x, i1 %c) {
-entry:
- br label %loop.header
-
-loop.header:
- %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
- br i1 %c, label %then, label %loop.latch
-
-then:
- %rem.1 = urem i32 10, %x
- br label %loop.latch
-
-loop.latch:
- %res = phi i32 [ 0, %loop.header ], [ %rem.1, %then ]
- %iv.next = add i32 %iv, 1
- %ec = icmp eq i32 %iv, 99
- br i1 %ec, label %exit, label %loop.header
-
-exit:
- ret i32 %res
-}
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