[llvm] [llvm] use 64-bit types for result of getDwarfRegNum (NFC) (PR #109492)
William G Hatch via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 20 16:26:32 PDT 2024
https://github.com/willghatch created https://github.com/llvm/llvm-project/pull/109492
The register encoding used by NVPTX and cuda-gdb basically use strings encoded as numbers. They are always within 64-bits, but typically outside of 32-bits, since they often need at least 5 characters.
This patch changes the signature of MCRegisterInfo::getDwarfRegNum and some related data structures to use 64-bit numbers to accommodate encodings like this.
Additionally, the MCRegisterInfo::getDwarfRegNum is marked as virtual, so that targets with peculiar dwarf register mapping schemes (such as NVPTX) can override its behavior.
>From a605d18af4beeabba91a963c2912edfb5ea303a7 Mon Sep 17 00:00:00 2001
From: William G Hatch <william at hatch.uno>
Date: Tue, 10 Sep 2024 14:47:57 -0600
Subject: [PATCH] [llvm] use 64-bit types for result of getDwarfRegNum (NFC)
The register encoding used by NVPTX and cuda-gdb basically use strings encoded as numbers. They are always within 64-bits, but typically outside of 32-bits, since they often need at least 5 characters.
This patch changes the signature of MCRegisterInfo::getDwarfRegNum and some related data structures to use 64-bit numbers to accommodate encodings like this.
Additionally, the MCRegisterInfo::getDwarfRegNum is marked as virtual, so that targets with peculiar dwarf register mapping schemes (such as NVPTX) can override its behavior.
---
llvm/include/llvm/MC/MCRegisterInfo.h | 6 +++---
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 4 ++--
llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp | 8 ++++----
llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h | 12 ++++++------
llvm/lib/MC/MCRegisterInfo.cpp | 14 +++++++++-----
llvm/lib/Target/Lanai/LanaiRegisterInfo.h | 2 --
6 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 11205a5a44c86c..4dd925dedd2bfa 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -418,15 +418,15 @@ class MCRegisterInfo {
/// number. Returns -1 if there is no equivalent value. The second
/// parameter allows targets to use different numberings for EH info and
/// debugging info.
- int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
+ virtual int64_t getDwarfRegNum(MCRegister RegNum, bool isEH) const;
/// Map a dwarf register back to a target register. Returns std::nullopt is
/// there is no mapping.
- std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
+ std::optional<unsigned> getLLVMRegNum(uint64_t RegNum, bool isEH) const;
/// Map a target EH register number to an equivalent DWARF register
/// number.
- int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
+ int64_t getDwarfRegNumFromDwarfEHRegNum(uint64_t RegNum) const;
/// Map a target register to an equivalent SEH register
/// number. Returns LLVM register number if there is no equivalent value.
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index ea3fed8817d893..6ebab029c1d38e 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -570,7 +570,7 @@ void DwarfDebug::constructAbstractSubprogramScopeDIE(DwarfCompileUnit &SrcCU,
/// debug expression to a register in the forwarded register worklist.
struct FwdRegParamInfo {
/// The described parameter register.
- unsigned ParamReg;
+ uint64_t ParamReg;
/// Debug expression that has been built up when walking through the
/// instruction chain that produces the parameter's value.
@@ -578,7 +578,7 @@ struct FwdRegParamInfo {
};
/// Register worklist for finding call site values.
-using FwdRegWorklist = MapVector<unsigned, SmallVector<FwdRegParamInfo, 2>>;
+using FwdRegWorklist = MapVector<uint64_t, SmallVector<FwdRegParamInfo, 2>>;
/// Container for the set of registers known to be clobbered on the path to a
/// call site.
using ClobberedRegSet = SmallSet<Register, 16>;
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index 9d6e1bb367bc85..08c762485b6527 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -40,7 +40,7 @@ void DwarfExpression::emitConstu(uint64_t Value) {
}
}
-void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
+void DwarfExpression::addReg(int64_t DwarfReg, const char *Comment) {
assert(DwarfReg >= 0 && "invalid negative dwarf register number");
assert((isUnknownLocation() || isRegisterLocation()) &&
"location description already locked down");
@@ -53,7 +53,7 @@ void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
}
}
-void DwarfExpression::addBReg(int DwarfReg, int Offset) {
+void DwarfExpression::addBReg(int64_t DwarfReg, int64_t Offset) {
assert(DwarfReg >= 0 && "invalid negative dwarf register number");
assert(!isRegisterLocation() && "location description already locked down");
if (DwarfReg < 32) {
@@ -65,7 +65,7 @@ void DwarfExpression::addBReg(int DwarfReg, int Offset) {
emitSigned(Offset);
}
-void DwarfExpression::addFBReg(int Offset) {
+void DwarfExpression::addFBReg(int64_t Offset) {
emitOp(dwarf::DW_OP_fbreg);
emitSigned(Offset);
}
@@ -108,7 +108,7 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
return false;
}
- int Reg = TRI.getDwarfRegNum(MachineReg, false);
+ int64_t Reg = TRI.getDwarfRegNum(MachineReg, false);
// If this is a valid register number, emit it.
if (Reg >= 0) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
index 4daa78b15b8e29..06809ab2638754 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
@@ -45,17 +45,17 @@ class DwarfExpression {
protected:
/// Holds information about all subregisters comprising a register location.
struct Register {
- int DwarfRegNo;
+ int64_t DwarfRegNo;
unsigned SubRegSize;
const char *Comment;
/// Create a full register, no extra DW_OP_piece operators necessary.
- static Register createRegister(int RegNo, const char *Comment) {
+ static Register createRegister(int64_t RegNo, const char *Comment) {
return {RegNo, 0, Comment};
}
/// Create a subregister that needs a DW_OP_piece operator with SizeInBits.
- static Register createSubRegister(int RegNo, unsigned SizeInBits,
+ static Register createSubRegister(int64_t RegNo, unsigned SizeInBits,
const char *Comment) {
return {RegNo, SizeInBits, Comment};
}
@@ -161,13 +161,13 @@ class DwarfExpression {
/// Emit a DW_OP_reg operation. Note that this is only legal inside a DWARF
/// register location description.
- void addReg(int DwarfReg, const char *Comment = nullptr);
+ void addReg(int64_t DwarfReg, const char *Comment = nullptr);
/// Emit a DW_OP_breg operation.
- void addBReg(int DwarfReg, int Offset);
+ void addBReg(int64_t DwarfReg, int64_t Offset);
/// Emit DW_OP_fbreg <Offset>.
- void addFBReg(int Offset);
+ void addFBReg(int64_t Offset);
/// Emit a partial DWARF register operation.
///
diff --git a/llvm/lib/MC/MCRegisterInfo.cpp b/llvm/lib/MC/MCRegisterInfo.cpp
index fde770a9c376c3..5ae333d2ab1f5e 100644
--- a/llvm/lib/MC/MCRegisterInfo.cpp
+++ b/llvm/lib/MC/MCRegisterInfo.cpp
@@ -141,7 +141,7 @@ unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,
return 0;
}
-int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
+int64_t MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
@@ -151,24 +151,28 @@ int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
if (I == M+Size || I->FromReg != RegNum)
return -1;
- return I->ToReg;
+ // Consumers need to be able to detect -1 and -2, but at various points
+ // the numbers move between unsigned and signed representations, as well as
+ // between 32- and 64-bit representations. We need to convert first to int
+ // before int64_t for proper sign handling.
+ return int64_t(int(I->ToReg));
}
-std::optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
+std::optional<unsigned> MCRegisterInfo::getLLVMRegNum(uint64_t RegNum,
bool isEH) const {
const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
if (!M)
return std::nullopt;
- DwarfLLVMRegPair Key = { RegNum, 0 };
+ DwarfLLVMRegPair Key = { unsigned(RegNum), 0 };
const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
if (I != M + Size && I->FromReg == RegNum)
return I->ToReg;
return std::nullopt;
}
-int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
+int64_t MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(uint64_t RegNum) const {
// On ELF platforms, DWARF EH register numbers are the same as DWARF
// other register numbers. On Darwin x86, they differ and so need to be
// mapped. The .cfi_* directives accept integer literals as well as
diff --git a/llvm/lib/Target/Lanai/LanaiRegisterInfo.h b/llvm/lib/Target/Lanai/LanaiRegisterInfo.h
index 5168dddd93019d..4ff74c5f4eb1e3 100644
--- a/llvm/lib/Target/Lanai/LanaiRegisterInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiRegisterInfo.h
@@ -43,8 +43,6 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
Register getFrameRegister(const MachineFunction &MF) const override;
Register getBaseRegister() const;
bool hasBasePointer(const MachineFunction &MF) const;
-
- int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
};
} // end namespace llvm
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