[llvm] [AMDGPU][MC] Instructions not to be supported in GFX940 (PR #109225)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 20 15:01:59 PDT 2024
https://github.com/jwanggit86 updated https://github.com/llvm/llvm-project/pull/109225
>From f9743fb591655bdbdce5e16e85f965f8dce94f12 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Wed, 18 Sep 2024 17:29:16 -0700
Subject: [PATCH 1/2] [AMDGPU][MC] Instructions not to be supported in GFX940
Buffer_store_lds_dword, buffer_wbinvl1, and buffer_wbinvl1_vol
are obsolete in GFX940 and should not be supported.
---
llvm/lib/Target/AMDGPU/BUFInstructions.td | 12 +++++++++---
llvm/test/MC/AMDGPU/gfx10_unsupported.s | 3 +++
llvm/test/MC/AMDGPU/gfx11_unsupported.s | 3 +++
llvm/test/MC/AMDGPU/gfx12_unsupported.s | 6 ++++++
llvm/test/MC/AMDGPU/gfx940_unsupported.s | 11 +++++++++++
5 files changed, 32 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/gfx940_unsupported.s
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index c6668b24f4ef67..1bc5cd140f14ec 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -3277,12 +3277,18 @@ defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_vi <0x6a>;
defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_vi <0x6b>;
defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_vi <0x6c>;
-defm BUFFER_STORE_LDS_DWORD : MUBUF_Real_vi_gfx90a <0x3d>;
+let AssemblerPredicate = isGFX8GFX9NotGFX90A in {
+defm BUFFER_STORE_LDS_DWORD : MUBUF_Real_vi <0x3d>;
+}
+
+let AssemblerPredicate = isGFX90AOnly in {
+defm BUFFER_STORE_LDS_DWORD : MUBUF_Real_gfx90a <0x3d>;
+}
-let AssemblerPredicate = isGFX8GFX9 in {
+let AssemblerPredicate = isGFX8GFX9NotGFX940 in {
defm BUFFER_WBINVL1 : MUBUF_Real_vi <0x3e>;
defm BUFFER_WBINVL1_VOL : MUBUF_Real_vi <0x3f>;
-} // End AssemblerPredicate = isGFX8GFX9
+} // End AssemblerPredicate = isGFX8GFX9NotGFX940
defm BUFFER_ATOMIC_PK_ADD_F16 : MUBUF_Real_Atomic_vi <0x4e>;
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported.s b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
index 1374417ac354b3..5a9f382d334ee4 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
@@ -215,6 +215,9 @@ buffer_store_d16_hi_format_x v1, off, s[12:15], -1 offset:4095
buffer_store_lds_dword s[4:7], -1 offset:4095 lds
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+buffer_wbinvl1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
buffer_wbinvl1_vol
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported.s b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
index 1e8d7684e942a6..c9756a068890e7 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
@@ -34,6 +34,9 @@ buffer_invl2
buffer_store_lds_dword s[4:7], -1 offset:4095 lds
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+buffer_wbinvl1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
buffer_wbinvl1_vol
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx12_unsupported.s b/llvm/test/MC/AMDGPU/gfx12_unsupported.s
index f0debbf052bcc1..c34cb9e29c1994 100644
--- a/llvm/test/MC/AMDGPU/gfx12_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx12_unsupported.s
@@ -232,9 +232,15 @@ buffer_gl0_inv
buffer_gl1_inv
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+buffer_store_lds_dword s[4:7], -1 offset:4095 lds
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
buffer_wbinvl1
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+buffer_wbinvl1_vol
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
flat_atomic_csub v1, v[0:1], v2 offset:64 th:TH_ATOMIC_RETURN
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction
diff --git a/llvm/test/MC/AMDGPU/gfx940_unsupported.s b/llvm/test/MC/AMDGPU/gfx940_unsupported.s
new file mode 100644
index 00000000000000..4ef53c7d952394
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx940_unsupported.s
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck --check-prefixes=CHECK --implicit-check-not=error: %s
+
+buffer_store_lds_dword s[4:7], -1 offset:4095 lds
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+buffer_wbinvl1
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+buffer_wbinvl1_vol
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
>From 2520948ce4a38c6a382471065b639db4746ad636 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Fri, 20 Sep 2024 15:00:56 -0700
Subject: [PATCH 2/2] Change subtarget predicate instead of assembler
predicate.
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 4 ++++
llvm/lib/Target/AMDGPU/BUFInstructions.td | 17 ++++++-----------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 5757ac0d4454d0..919e698e76b33b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1900,6 +1900,10 @@ def isGFX940Plus :
Predicate<"Subtarget->hasGFX940Insts()">,
AssemblerPredicate<(all_of FeatureGFX940Insts)>;
+def isNotGFX940Plus :
+ Predicate<"!Subtarget->hasGFX940Insts()">,
+ AssemblerPredicate<(all_of (not FeatureGFX940Insts))>;
+
def isGFX8GFX9NotGFX940 :
Predicate<"!Subtarget->hasGFX940Insts() &&"
"(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 1bc5cd140f14ec..bb3e00d76ccb1c 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -1132,7 +1132,7 @@ let OtherPredicates = [HasGFX10_BEncoding] in {
>;
}
-let SubtargetPredicate = isGFX8GFX9 in {
+let SubtargetPredicate = isGFX8GFX9NotGFX940 in {
def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">;
}
@@ -1214,7 +1214,7 @@ defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores <
} // End HasD16LoadStore
-let SubtargetPredicate = isNotGFX12Plus in
+let SubtargetPredicate = isNotGFX940Plus in
def BUFFER_WBINVL1 : MUBUF_Invalidate <
"buffer_wbinvl1", int_amdgcn_buffer_wbinvl1
>;
@@ -1297,6 +1297,7 @@ let SubtargetPredicate = isGFX7Plus in {
// Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===//
+let SubtargetPredicate = isNotGFX940Plus in
def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
int_amdgcn_buffer_wbinvl1_vol>;
@@ -3277,18 +3278,12 @@ defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_vi <0x6a>;
defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_vi <0x6b>;
defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_vi <0x6c>;
-let AssemblerPredicate = isGFX8GFX9NotGFX90A in {
-defm BUFFER_STORE_LDS_DWORD : MUBUF_Real_vi <0x3d>;
-}
-
-let AssemblerPredicate = isGFX90AOnly in {
-defm BUFFER_STORE_LDS_DWORD : MUBUF_Real_gfx90a <0x3d>;
-}
+defm BUFFER_STORE_LDS_DWORD : MUBUF_Real_vi_gfx90a <0x3d>;
-let AssemblerPredicate = isGFX8GFX9NotGFX940 in {
+let AssemblerPredicate = isGFX8GFX9 in {
defm BUFFER_WBINVL1 : MUBUF_Real_vi <0x3e>;
defm BUFFER_WBINVL1_VOL : MUBUF_Real_vi <0x3f>;
-} // End AssemblerPredicate = isGFX8GFX9NotGFX940
+} // End AssemblerPredicate = isGFX8GFX9
defm BUFFER_ATOMIC_PK_ADD_F16 : MUBUF_Real_Atomic_vi <0x4e>;
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