[llvm] [RISCV][GISEL] Legalize G_EXTRACT_SUBVECTOR (PR #109426)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 20 11:56:16 PDT 2024
================
@@ -931,6 +935,133 @@ bool RISCVLegalizerInfo::legalizeSplatVector(MachineInstr &MI,
return true;
}
+static LLT getLMUL1Ty(LLT VecTy) {
+ assert(VecTy.getElementType().getSizeInBits() <= 64 &&
+ "Unexpected vector LLT");
+ return LLT::scalable_vector(RISCV::RVVBitsPerBlock /
+ VecTy.getElementType().getSizeInBits(),
+ VecTy.getElementType());
+}
+
+bool RISCVLegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
+ MachineIRBuilder &MIB) const {
+ GExtractSubvector &ES = cast<GExtractSubvector>(MI);
+
+ MachineRegisterInfo &MRI = *MIB.getMRI();
+
+ Register Dst = ES.getReg(0);
+ Register Src = ES.getSrcVec();
+ uint64_t Idx = ES.getIndexImm();
+
+ // Only support vectors using custom legalization. We know the DstTy is a
+ // vector since we used that to decide whether to custom legalize or not.
+ LLT BigTy = MRI.getType(Src);
+ if (BigTy.isScalar())
+ return false;
----------------
arsenm wrote:
This is malformed MIR
https://github.com/llvm/llvm-project/pull/109426
More information about the llvm-commits
mailing list