[llvm] [RISCV] Add 16 bit GPR sub-register for Zhinx. (PR #107446)

[Craig Topper via llvm-commits]

topperc wrote:

@asb can you re-review this? I added compressed versions of the load/store CodeGenOnly instructions, a pseudo for mv, updated MakeCompressible, MergeBaseOffset.

https://github.com/llvm/llvm-project/pull/107446