[llvm] [NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (PR #109417)
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llvm-commits at lists.llvm.org
Fri Sep 20 06:20:31 PDT 2024
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git-clang-format --diff efdb3ae23247850d3886e3708400f0d991ed59e1 b3a4bff74f67be5185641169fa295bceb4a872ce --extensions cpp,h -- llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h llvm/include/llvm/Analysis/SparsePropagation.h llvm/lib/Analysis/MemoryDependenceAnalysis.cpp llvm/lib/Analysis/ScalarEvolution.cpp llvm/lib/CodeGen/CalcSpillWeights.cpp llvm/lib/CodeGen/MachineLICM.cpp llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h llvm/lib/Transforms/IPO/CalledValuePropagation.cpp llvm/lib/Transforms/Utils/BasicBlockUtils.cpp llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
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View the diff from clang-format here.
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diff --git a/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h b/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
index c31e663498..700343561f 100644
--- a/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
+++ b/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
@@ -487,14 +487,12 @@ private:
MemDepResult getCallDependencyFrom(CallBase *Call, bool isReadOnlyCall,
BasicBlock::iterator ScanIt,
BasicBlock *BB);
- bool getNonLocalPointerDepFromBB(Instruction *QueryInst,
- const PHITransAddr &Pointer,
- const MemoryLocation &Loc, bool isLoad,
- BasicBlock *BB,
- SmallVectorImpl<NonLocalDepResult> &Result,
- SmallDenseMap<BasicBlock *, Value *, 16> &Visited,
- bool SkipFirstBlock = false,
- bool IsIncomplete = false);
+ bool getNonLocalPointerDepFromBB(
+ Instruction *QueryInst, const PHITransAddr &Pointer,
+ const MemoryLocation &Loc, bool isLoad, BasicBlock *BB,
+ SmallVectorImpl<NonLocalDepResult> &Result,
+ SmallDenseMap<BasicBlock *, Value *, 16> &Visited,
+ bool SkipFirstBlock = false, bool IsIncomplete = false);
MemDepResult getNonLocalInfoForBlock(Instruction *QueryInst,
const MemoryLocation &Loc, bool isLoad,
BasicBlock *BB, NonLocalDepInfo *Cache,
diff --git a/llvm/include/llvm/Analysis/SparsePropagation.h b/llvm/include/llvm/Analysis/SparsePropagation.h
index 194f4787a8..cc79870229 100644
--- a/llvm/include/llvm/Analysis/SparsePropagation.h
+++ b/llvm/include/llvm/Analysis/SparsePropagation.h
@@ -87,10 +87,9 @@ public:
/// ComputeInstructionState - Compute the LatticeKeys that change as a result
/// of executing instruction \p I. Their associated LatticeVals are store in
/// \p ChangedValues.
- virtual void
- ComputeInstructionState(Instruction &I,
- SmallDenseMap<LatticeKey, LatticeVal, 16> &ChangedValues,
- SparseSolver<LatticeKey, LatticeVal> &SS) = 0;
+ virtual void ComputeInstructionState(
+ Instruction &I, SmallDenseMap<LatticeKey, LatticeVal, 16> &ChangedValues,
+ SparseSolver<LatticeKey, LatticeVal> &SS) = 0;
/// PrintLatticeVal - Render the given LatticeVal to the specified stream.
virtual void PrintLatticeVal(LatticeVal LV, raw_ostream &OS);
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index b2c2944c57..d2ffda254d 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -2254,12 +2254,10 @@ const SCEV *ScalarEvolution::getAnyExtendExpr(const SCEV *Op,
/// may be exposed. This helps getAddRecExpr short-circuit extra work in
/// the common case where no interesting opportunities are present, and
/// is also used as a check to avoid infinite recursion.
-static bool
-CollectAddOperandsWithScales(SmallDenseMap<const SCEV *, APInt, 16> &M,
- SmallVectorImpl<const SCEV *> &NewOps,
- APInt &AccumulatedConstant,
- ArrayRef<const SCEV *> Ops, const APInt &Scale,
- ScalarEvolution &SE) {
+static bool CollectAddOperandsWithScales(
+ SmallDenseMap<const SCEV *, APInt, 16> &M,
+ SmallVectorImpl<const SCEV *> &NewOps, APInt &AccumulatedConstant,
+ ArrayRef<const SCEV *> Ops, const APInt &Scale, ScalarEvolution &SE) {
bool Interesting = false;
// Iterate over the add operands. They are sorted, with constants first.
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index c1f3d5ac4f..3289a69222 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -265,8 +265,8 @@ namespace {
void InitRegPressure(MachineBasicBlock *BB);
SmallDenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
- bool ConsiderSeen,
- bool ConsiderUnseenAsDef);
+ bool ConsiderSeen,
+ bool ConsiderUnseenAsDef);
void UpdateRegPressure(const MachineInstr *MI,
bool ConsiderUnseenAsDef = false);
@@ -1248,7 +1248,7 @@ bool MachineLICMImpl::IsCheapInstruction(MachineInstr &MI) const {
/// Visit BBs from header to current BB, check if hoisting an instruction of the
/// given cost matrix can cause high register pressure.
bool MachineLICMImpl::CanCauseHighRegPressure(
- const SmallDenseMap<unsigned, int>& Cost, bool CheapInstr) {
+ const SmallDenseMap<unsigned, int> &Cost, bool CheapInstr) {
for (const auto &RPIdAndCost : Cost) {
if (RPIdAndCost.second <= 0)
continue;
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 738319d44d..bd834871c9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -82,8 +82,7 @@ static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
/// implicit physical register output.
void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
- Register SrcReg,
- VRBaseMapType &VRBaseMap) {
+ Register SrcReg, VRBaseMapType &VRBaseMap) {
Register VRBase;
if (SrcReg.isVirtual()) {
// Just use the input register directly!
@@ -184,10 +183,10 @@ void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
}
void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
- MachineInstrBuilder &MIB,
- const MCInstrDesc &II,
- bool IsClone, bool IsCloned,
- VRBaseMapType &VRBaseMap) {
+ MachineInstrBuilder &MIB,
+ const MCInstrDesc &II, bool IsClone,
+ bool IsCloned,
+ VRBaseMapType &VRBaseMap) {
assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
@@ -265,8 +264,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
-Register InstrEmitter::getVR(SDValue Op,
- VRBaseMapType &VRBaseMap) {
+Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use.
@@ -313,13 +311,10 @@ static bool isConvergenceCtrlMachineOp(SDValue Op) {
/// AddRegisterOperand - Add the specified register as an operand to the
/// specified machine instr. Insert register copies if the register is
/// not in the required register class.
-void
-InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
- SDValue Op,
- unsigned IIOpNum,
- const MCInstrDesc *II,
- VRBaseMapType &VRBaseMap,
- bool IsDebug, bool IsClone, bool IsCloned) {
+void InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, SDValue Op,
+ unsigned IIOpNum, const MCInstrDesc *II,
+ VRBaseMapType &VRBaseMap, bool IsDebug,
+ bool IsClone, bool IsCloned) {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue &&
"Chain and glue operands should occur at end of operand list!");
@@ -395,12 +390,10 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
/// AddOperand - Add the specified operand to the specified machine instr. II
/// specifies the instruction information for the node, and IIOpNum is the
/// operand number (in the II) that we are adding.
-void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
- SDValue Op,
- unsigned IIOpNum,
- const MCInstrDesc *II,
- VRBaseMapType &VRBaseMap,
- bool IsDebug, bool IsClone, bool IsCloned) {
+void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
+ unsigned IIOpNum, const MCInstrDesc *II,
+ VRBaseMapType &VRBaseMap, bool IsDebug,
+ bool IsClone, bool IsCloned) {
if (Op.isMachineOpcode()) {
AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
IsDebug, IsClone, IsCloned);
@@ -499,8 +492,7 @@ Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
/// EmitSubregNode - Generate machine code for subreg nodes.
///
-void InstrEmitter::EmitSubregNode(SDNode *Node,
- VRBaseMapType &VRBaseMap,
+void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
bool IsClone, bool IsCloned) {
Register VRBase;
unsigned Opc = Node->getMachineOpcode();
@@ -632,9 +624,8 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
/// COPY_TO_REGCLASS is just a normal copy, except that the destination
/// register is constrained to be in a particular register class.
///
-void
-InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
- VRBaseMapType &VRBaseMap) {
+void InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
+ VRBaseMapType &VRBaseMap) {
Register VReg = getVR(Node->getOperand(0), VRBaseMap);
// Create the new VReg in the destination class and emit a copy.
@@ -653,9 +644,8 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
///
-void InstrEmitter::EmitRegSequence(SDNode *Node,
- VRBaseMapType &VRBaseMap,
- bool IsClone, bool IsCloned) {
+void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
+ bool IsClone, bool IsCloned) {
unsigned DstRCIdx = Node->getConstantOperandVal(0);
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
@@ -701,9 +691,8 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
///
-MachineInstr *
-InstrEmitter::EmitDbgValue(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap) {
+MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD,
+ VRBaseMapType &VRBaseMap) {
DebugLoc DL = SD->getDebugLoc();
assert(cast<DILocalVariable>(SD->getVariable())
->isValidLocationForIntrinsic(DL) &&
@@ -752,10 +741,10 @@ MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op) {
/* SubReg */ 0, /* isDebug */ true);
}
-void InstrEmitter::AddDbgValueLocationOps(
- MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
- ArrayRef<SDDbgOperand> LocationOps,
- VRBaseMapType &VRBaseMap) {
+void InstrEmitter::AddDbgValueLocationOps(MachineInstrBuilder &MIB,
+ const MCInstrDesc &DbgValDesc,
+ ArrayRef<SDDbgOperand> LocationOps,
+ VRBaseMapType &VRBaseMap) {
for (const SDDbgOperand &Op : LocationOps) {
switch (Op.getKind()) {
case SDDbgOperand::FRAMEIX:
@@ -784,9 +773,8 @@ void InstrEmitter::AddDbgValueLocationOps(
}
}
-MachineInstr *
-InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap) {
+MachineInstr *InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
+ VRBaseMapType &VRBaseMap) {
MDNode *Var = SD->getVariable();
const DIExpression *Expr = (DIExpression *)SD->getExpression();
DebugLoc DL = SD->getDebugLoc();
@@ -926,9 +914,8 @@ MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
return BuildMI(*MF, DL, Desc, false, 0U, Var, Expr);
}
-MachineInstr *
-InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap) {
+MachineInstr *InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
+ VRBaseMapType &VRBaseMap) {
MDNode *Var = SD->getVariable();
DIExpression *Expr = SD->getExpression();
DebugLoc DL = SD->getDebugLoc();
@@ -942,9 +929,8 @@ InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
return &*MIB;
}
-MachineInstr *
-InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap) {
+MachineInstr *InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
+ VRBaseMapType &VRBaseMap) {
MDNode *Var = SD->getVariable();
DIExpression *Expr = SD->getExpression();
DebugLoc DL = SD->getDebugLoc();
@@ -994,9 +980,8 @@ InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
/// EmitMachineNode - Generate machine code for a target-specific node and
/// needed dependencies.
///
-void InstrEmitter::
-EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
- VRBaseMapType &VRBaseMap) {
+void InstrEmitter::EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
+ VRBaseMapType &VRBaseMap) {
unsigned Opc = Node->getMachineOpcode();
// Handle subreg insert/extract specially
@@ -1236,9 +1221,8 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
/// EmitSpecialNode - Generate machine code for a target-independent node and
/// needed dependencies.
-void InstrEmitter::
-EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
- VRBaseMapType &VRBaseMap) {
+void InstrEmitter::EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
+ VRBaseMapType &VRBaseMap) {
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
index fcfcaa8d35..047e8930bb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
@@ -49,11 +49,9 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
Register SrcReg, VRBaseMapType &VRBaseMap);
- void CreateVirtualRegisters(SDNode *Node,
- MachineInstrBuilder &MIB,
- const MCInstrDesc &II,
- bool IsClone, bool IsCloned,
- VRBaseMapType &VRBaseMap);
+ void CreateVirtualRegisters(SDNode *Node, MachineInstrBuilder &MIB,
+ const MCInstrDesc &II, bool IsClone,
+ bool IsCloned, VRBaseMapType &VRBaseMap);
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
@@ -62,23 +60,18 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
/// AddRegisterOperand - Add the specified register as an operand to the
/// specified machine instr. Insert register copies if the register is
/// not in the required register class.
- void AddRegisterOperand(MachineInstrBuilder &MIB,
- SDValue Op,
- unsigned IIOpNum,
- const MCInstrDesc *II,
- VRBaseMapType &VRBaseMap,
- bool IsDebug, bool IsClone, bool IsCloned);
+ void AddRegisterOperand(MachineInstrBuilder &MIB, SDValue Op,
+ unsigned IIOpNum, const MCInstrDesc *II,
+ VRBaseMapType &VRBaseMap, bool IsDebug, bool IsClone,
+ bool IsCloned);
/// AddOperand - Add the specified operand to the specified machine instr. II
/// specifies the instruction information for the node, and IIOpNum is the
/// operand number (in the II) that we are adding. IIOpNum and II are used for
/// assertions only.
- void AddOperand(MachineInstrBuilder &MIB,
- SDValue Op,
- unsigned IIOpNum,
- const MCInstrDesc *II,
- VRBaseMapType &VRBaseMap,
- bool IsDebug, bool IsClone, bool IsCloned);
+ void AddOperand(MachineInstrBuilder &MIB, SDValue Op, unsigned IIOpNum,
+ const MCInstrDesc *II, VRBaseMapType &VRBaseMap, bool IsDebug,
+ bool IsClone, bool IsCloned);
/// ConstrainForSubReg - Try to constrain VReg to a register class that
/// supports SubIdx sub-registers. Emit a copy if that isn't possible.
@@ -88,20 +81,20 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
/// EmitSubregNode - Generate machine code for subreg nodes.
///
- void EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
- bool IsClone, bool IsCloned);
+ void EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap, bool IsClone,
+ bool IsCloned);
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
/// COPY_TO_REGCLASS is just a normal copy, except that the destination
/// register is constrained to be in a particular register class.
///
- void EmitCopyToRegClassNode(SDNode *Node,
- VRBaseMapType &VRBaseMap);
+ void EmitCopyToRegClassNode(SDNode *Node, VRBaseMapType &VRBaseMap);
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
///
- void EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
- bool IsClone, bool IsCloned);
+ void EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap, bool IsClone,
+ bool IsCloned);
+
public:
/// CountResults - The results of target nodes have register or immediate
/// operands first, then an optional chain, and optional flag operands
@@ -115,25 +108,22 @@ public:
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
///
- MachineInstr *EmitDbgValue(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap);
+ MachineInstr *EmitDbgValue(SDDbgValue *SD, VRBaseMapType &VRBaseMap);
/// Emit a dbg_value as a DBG_INSTR_REF. May produce DBG_VALUE $noreg instead
/// if there is no variable location; alternately a half-formed DBG_INSTR_REF
/// that refers to a virtual register and is corrected later in isel.
- MachineInstr *EmitDbgInstrRef(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap);
+ MachineInstr *EmitDbgInstrRef(SDDbgValue *SD, VRBaseMapType &VRBaseMap);
/// Emit a DBG_VALUE $noreg, indicating a variable has no location.
MachineInstr *EmitDbgNoLocation(SDDbgValue *SD);
/// Emit a DBG_VALUE_LIST from the operands to SDDbgValue.
- MachineInstr *EmitDbgValueList(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap);
+ MachineInstr *EmitDbgValueList(SDDbgValue *SD, VRBaseMapType &VRBaseMap);
/// Emit a DBG_VALUE from the operands to SDDbgValue.
MachineInstr *EmitDbgValueFromSingleOp(SDDbgValue *SD,
- VRBaseMapType &VRBaseMap);
+ VRBaseMapType &VRBaseMap);
/// Generate machine instruction for a dbg_label node.
MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 99016d8013..cefcacdecd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -736,8 +736,9 @@ void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
/// ProcessSDDbgValues - Process SDDbgValues associated with this node.
static void
ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
- SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
- SmallDenseMap<SDValue, Register, 16> &VRBaseMap, unsigned Order) {
+ SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders,
+ SmallDenseMap<SDValue, Register, 16> &VRBaseMap,
+ unsigned Order) {
if (!N->getHasDebugValue())
return;
@@ -807,9 +808,9 @@ ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
}
-void ScheduleDAGSDNodes::
-EmitPhysRegCopy(SUnit *SU, SmallDenseMap<SUnit*, Register, 16> &VRBaseMap,
- MachineBasicBlock::iterator InsertPos) {
+void ScheduleDAGSDNodes::EmitPhysRegCopy(
+ SUnit *SU, SmallDenseMap<SUnit *, Register, 16> &VRBaseMap,
+ MachineBasicBlock::iterator InsertPos) {
for (const SDep &Pred : SU->Preds) {
if (Pred.isCtrl())
continue; // ignore chain preds
@@ -852,7 +853,7 @@ MachineBasicBlock *ScheduleDAGSDNodes::
EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
SmallDenseMap<SDValue, Register, 16> VRBaseMap;
- SmallDenseMap<SUnit*, Register, 16> CopyVRBaseMap;
+ SmallDenseMap<SUnit *, Register, 16> CopyVRBaseMap;
SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
SmallSet<Register, 8> Seen;
bool HasDbg = DAG->hasDebugValues();
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index 2811b41fc7..b7d25c6ccc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -184,7 +184,8 @@ class InstrItineraryData;
void BuildSchedUnits();
void AddSchedEdges();
- void EmitPhysRegCopy(SUnit *SU, SmallDenseMap<SUnit*, Register, 16> &VRBaseMap,
+ void EmitPhysRegCopy(SUnit *SU,
+ SmallDenseMap<SUnit *, Register, 16> &VRBaseMap,
MachineBasicBlock::iterator InsertPos);
};
diff --git a/llvm/lib/Transforms/IPO/CalledValuePropagation.cpp b/llvm/lib/Transforms/IPO/CalledValuePropagation.cpp
index a75a0bbc53..66ae0706d6 100644
--- a/llvm/lib/Transforms/IPO/CalledValuePropagation.cpp
+++ b/llvm/lib/Transforms/IPO/CalledValuePropagation.cpp
@@ -169,7 +169,8 @@ public:
/// just a few kinds of instructions since we're only propagating values that
/// can be called.
void ComputeInstructionState(
- Instruction &I, SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
+ Instruction &I,
+ SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) override {
switch (I.getOpcode()) {
case Instruction::Call:
@@ -238,9 +239,10 @@ private:
/// Handle return instructions. The function's return state is the merge of
/// the returned value state and the function's return state.
- void visitReturn(ReturnInst &I,
- SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
- SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
+ void
+ visitReturn(ReturnInst &I,
+ SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
+ SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
Function *F = I.getParent()->getParent();
if (F->getReturnType()->isVoidTy())
return;
@@ -254,9 +256,10 @@ private:
/// the merge of the argument state with the call sites corresponding actual
/// argument state. The call site state is the merge of the call site state
/// with the returned value state of the called function.
- void visitCallBase(CallBase &CB,
- SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
- SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
+ void
+ visitCallBase(CallBase &CB,
+ SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
+ SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
Function *F = CB.getCalledFunction();
auto RegI = CVPLatticeKey(&CB, IPOGrouping::Register);
@@ -298,9 +301,10 @@ private:
/// Handle select instructions. The select instruction state is the merge the
/// true and false value states.
- void visitSelect(SelectInst &I,
- SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
- SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
+ void
+ visitSelect(SelectInst &I,
+ SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
+ SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
auto RegI = CVPLatticeKey(&I, IPOGrouping::Register);
auto RegT = CVPLatticeKey(I.getTrueValue(), IPOGrouping::Register);
auto RegF = CVPLatticeKey(I.getFalseValue(), IPOGrouping::Register);
@@ -327,9 +331,10 @@ private:
/// Handle store instructions. If the pointer operand of the store is a
/// global variable, we attempt to track the value. The global variable state
/// is the merge of the stored value state with the global variable state.
- void visitStore(StoreInst &I,
- SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
- SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
+ void
+ visitStore(StoreInst &I,
+ SmallDenseMap<CVPLatticeKey, CVPLatticeVal, 16> &ChangedValues,
+ SparseSolver<CVPLatticeKey, CVPLatticeVal> &SS) {
auto *GV = dyn_cast<GlobalVariable>(I.getPointerOperand());
if (!GV)
return;
diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index 77f4f2822d..7bffd4da75 100644
--- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -503,7 +503,8 @@ static bool removeRedundantDbgInstrsUsingBackwardScan(BasicBlock *BB) {
static bool
DbgVariableRecordsRemoveRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) {
SmallVector<DbgVariableRecord *, 8> ToBeRemoved;
- SmallDenseMap<DebugVariable, std::pair<SmallVector<Value *, 4>, DIExpression *>, 4>
+ SmallDenseMap<DebugVariable,
+ std::pair<SmallVector<Value *, 4>, DIExpression *>, 4>
VariableMap;
for (auto &I : *BB) {
for (DbgVariableRecord &DVR : filterDbgVars(I.getDbgRecordRange())) {
@@ -584,7 +585,8 @@ static bool removeRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) {
return DbgVariableRecordsRemoveRedundantDbgInstrsUsingForwardScan(BB);
SmallVector<DbgValueInst *, 8> ToBeRemoved;
- SmallDenseMap<DebugVariable, std::pair<SmallVector<Value *, 4>, DIExpression *>, 4>
+ SmallDenseMap<DebugVariable,
+ std::pair<SmallVector<Value *, 4>, DIExpression *>, 4>
VariableMap;
for (auto &I : *BB) {
if (DbgValueInst *DVI = dyn_cast<DbgValueInst>(&I)) {
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 068d352dc9..497043ec97 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -17726,7 +17726,8 @@ public:
for (Value *V : Candidates)
TrackedVals.try_emplace(V, V);
- auto At = [](SmallMapVector<Value *, unsigned, 16> &MV, Value *V) -> unsigned & {
+ auto At = [](SmallMapVector<Value *, unsigned, 16> &MV,
+ Value *V) -> unsigned & {
auto *It = MV.find(V);
assert(It != MV.end() && "Unable to find given key.");
return It->second;
@@ -18424,10 +18425,10 @@ private:
/// Emits actual operation for the scalar identity values, found during
/// horizontal reduction analysis.
- Value *emitReusedOps(Value *VectorizedValue, IRBuilderBase &Builder,
- BoUpSLP &R,
- const SmallMapVector<Value *, unsigned, 16> &SameValuesCounter,
- const DenseMap<Value *, Value *> &TrackedToOrig) {
+ Value *
+ emitReusedOps(Value *VectorizedValue, IRBuilderBase &Builder, BoUpSLP &R,
+ const SmallMapVector<Value *, unsigned, 16> &SameValuesCounter,
+ const DenseMap<Value *, Value *> &TrackedToOrig) {
assert(IsSupportedHorRdxIdentityOp &&
"The optimization of matched scalar identity horizontal reductions "
"must be supported.");
``````````
</details>
https://github.com/llvm/llvm-project/pull/109417
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