[llvm] 3bcffe5 - [X86] Fix MSVC implicit shift extension warning.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-09-20T13:37:59+01:00
New Revision: 3bcffe5ccc694d7c40f4bc84bd9ced1cc0e30d5c

URL: https://github.com/llvm/llvm-project/commit/3bcffe5ccc694d7c40f4bc84bd9ced1cc0e30d5c
DIFF: https://github.com/llvm/llvm-project/commit/3bcffe5ccc694d7c40f4bc84bd9ced1cc0e30d5c.diff

LOG: [X86] Fix MSVC implicit shift extension warning.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4c6a323ffba6ae..c5dc3ea17f72c3 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30007,7 +30007,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
       // This is equal to Masked - 2*SignBitMask which will correctly sign
       // extend our result.
       SDValue CstHighBit =
-          DAG.getConstant(1 << (EltSizeInBits - 1), dl, NarrowScalarVT);
+          DAG.getConstant(1ULL << (EltSizeInBits - 1), dl, NarrowScalarVT);
       SDValue SplatHighBit = DAG.getSplat(VT, dl, CstHighBit);
       // This does not induce recursion, all operands are constants.
       SDValue SignBitMask = DAG.getNode(LogicalOpc, dl, VT, SplatHighBit, Amt);