[llvm] [AMDGPU] Use Lo_32 and Hi_32 helpers (NFC) (PR #109413)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 20 05:13:20 PDT 2024
https://github.com/nikic created https://github.com/llvm/llvm-project/pull/109413
None
>From 98bff60f9a85d78ab32d25d96ef8fee41746c612 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Fri, 20 Sep 2024 14:08:26 +0200
Subject: [PATCH] [AMDGPU] Use Lo_32 and Hi_32 helpers (NFC)
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 12 ++++++------
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 ++--
llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 8 ++++----
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++--
6 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 380dc7d3312f32..d186ef896ea406 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -424,10 +424,10 @@ MachineSDNode *AMDGPUDAGToDAGISel::buildSMovImm64(SDLoc &DL, uint64_t Imm,
EVT VT) const {
SDNode *Lo = CurDAG->getMachineNode(
AMDGPU::S_MOV_B32, DL, MVT::i32,
- CurDAG->getTargetConstant(Imm & 0xFFFFFFFF, DL, MVT::i32));
- SDNode *Hi =
- CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
- CurDAG->getTargetConstant(Imm >> 32, DL, MVT::i32));
+ CurDAG->getTargetConstant(Lo_32(Imm), DL, MVT::i32));
+ SDNode *Hi = CurDAG->getMachineNode(
+ AMDGPU::S_MOV_B32, DL, MVT::i32,
+ CurDAG->getTargetConstant(Hi_32(Imm), DL, MVT::i32));
const SDValue Ops[] = {
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
@@ -1805,8 +1805,8 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
// single VALU instruction to materialize zero. Otherwise it is less
// instructions to perform VALU adds with immediates or inline literals.
unsigned NumLiterals =
- !TII->isInlineConstant(APInt(32, COffsetVal & 0xffffffff)) +
- !TII->isInlineConstant(APInt(32, COffsetVal >> 32));
+ !TII->isInlineConstant(APInt(32, Lo_32(COffsetVal))) +
+ !TII->isInlineConstant(APInt(32, Hi_32(COffsetVal)));
if (Subtarget->getConstantBusLimit(AMDGPU::V_ADD_U32_e64) > NumLiterals)
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 53085d423cefb8..febf0711c7d574 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4376,8 +4376,8 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
// single VALU instruction to materialize zero. Otherwise it is less
// instructions to perform VALU adds with immediates or inline literals.
unsigned NumLiterals =
- !TII.isInlineConstant(APInt(32, ConstOffset & 0xffffffff)) +
- !TII.isInlineConstant(APInt(32, ConstOffset >> 32));
+ !TII.isInlineConstant(APInt(32, Lo_32(ConstOffset))) +
+ !TII.isInlineConstant(APInt(32, Hi_32(ConstOffset)));
if (STI.getConstantBusLimit(AMDGPU::V_ADD_U32_e64) > NumLiterals)
return std::nullopt;
}
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index bab3f8a08781da..f973924ae58ea2 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2394,7 +2394,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
return;
}
- Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));
+ Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
setImmKindLiteral();
return;
@@ -2421,7 +2421,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
if (isSafeTruncation(Val, 16) &&
AMDGPU::isInlinableIntLiteral(static_cast<int16_t>(Val))) {
- Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));
+ Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
setImmKindConst();
return;
}
diff --git a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
index 4467836cffc566..a6112b39325eee 100644
--- a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
@@ -159,7 +159,7 @@ bool GCNPreRAOptimizations::processReg(Register Reg) {
if (Def0)
return false;
Def0 = &I;
- Init |= I.getOperand(1).getImm() & 0xffffffff;
+ Init |= Lo_32(I.getOperand(1).getImm());
break;
case AMDGPU::sub1:
if (Def1)
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index dfdc7ad32b00c7..2c67c4aedfe475 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -829,12 +829,12 @@ void SIFrameLowering::emitEntryFunctionScratchRsrcRegSetup(
}
BuildMI(MBB, I, DL, SMovB32, Rsrc2)
- .addImm(Rsrc23 & 0xffffffff)
- .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
+ .addImm(Lo_32(Rsrc23))
+ .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
BuildMI(MBB, I, DL, SMovB32, Rsrc3)
- .addImm(Rsrc23 >> 32)
- .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
+ .addImm(Hi_32(Rsrc23))
+ .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
} else if (ST.isAmdHsaOrMesa(Fn)) {
assert(PreloadedScratchRsrcReg);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c6a9a627d457e7..163cf42fc4474d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6554,11 +6554,11 @@ extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
// SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
- .addImm(RsrcDataFormat & 0xFFFFFFFF);
+ .addImm(Lo_32(RsrcDataFormat));
// SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
- .addImm(RsrcDataFormat >> 32);
+ .addImm(Hi_32(RsrcDataFormat));
// NewSRsrc = {Zero64, SRsrcFormat}
BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
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