[llvm] [LoongArch] Pass 'half' in the lower 16 bits of an f32 value when F extension is enabled (PR #109368)

[Xi Ruoyao via llvm-commits]

xry111 wrote:

We don't have an "F extension."  That's a concept of RISC-V and we call it "basic floating-point instructions."

And the ABI isn't necessarily aligning to the ISA capability (i.e. you can still use LP64S ABI on a CPU with floating-point instructions) so it's better to re-title this `Pass 'half' in the lower 16 bits of an f32 value with F/D ABI`.

https://github.com/llvm/llvm-project/pull/109368