[llvm] [RISCV] Set the isMoveReg flag for FMV_X_W (PR #109378)

[Shao-Ce SUN via llvm-commits]

https://github.com/sunshaoce created https://github.com/llvm/llvm-project/pull/109378

It seems that other `mv` instructions should do this, but llvm's tests have not changed.

>From 5b4f8b8e73736ce09f66a2394204c5ac24e40241 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN <sunshaoce at outlook.com>
Date: Fri, 20 Sep 2024 14:05:10 +0800
Subject: [PATCH] [RISCV] Set the isMoveReg flag for FMV_X_W

---
 llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 4 ++--
 llvm/test/CodeGen/RISCV/select-const.ll  | 4 ----
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index a00acb372dc2a2..4bafd5c86c12c3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -388,11 +388,11 @@ foreach Ext = FExts in {
 } // foreach Ext = FExts
 
 let Predicates = [HasStdExtF], mayRaiseFPException = 0,
-    IsSignExtendingOpW = 1 in
+    IsSignExtendingOpW = 1, isMoveReg = 1 in
 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 
-let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
+let Predicates = [HasStdExtF], mayRaiseFPException = 0, isMoveReg = 1 in
 def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
               Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
 
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
index 792df6236ddc0e..a8716e6afb80c3 100644
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -102,8 +102,6 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
 ; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    lui a0, 263168
 ; RV32IF-NEXT:  .LBB4_3:
-; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fmv.x.w a0, fa5
 ; RV32IF-NEXT:    ret
 ;
 ; RV64I-LABEL: select_const_fp:
@@ -125,8 +123,6 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
 ; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    lui a0, 263168
 ; RV64IFD-NEXT:  .LBB4_3:
-; RV64IFD-NEXT:    fmv.w.x fa5, a0
-; RV64IFD-NEXT:    fmv.x.w a0, fa5
 ; RV64IFD-NEXT:    ret
   %1 = select i1 %a, float 3.0, float 4.0
   ret float %1