[llvm] [AArch64][CostModel] Reduce the cost of fadd reduction with fast flag (PR #108791)

[David Green via llvm-commits]

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@@ -4147,6 +4147,22 @@ AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
   switch (ISD) {
   default:
     break;
+  case ISD::FADD: {
+    if (MTy.isVector()) {
+      // FIXME: Consider cases where the number of vector elements is not power
+      // of 2.
+      const unsigned NElts = MTy.getVectorNumElements();
+      if (ValTy->getElementCount().getFixedValue() >= 2 && NElts >= 2 &&
+          isPowerOf2_32(NElts)) {
+        // Reduction corresponding to series of fadd instructions is lowered to
+        // series of faddp instructions. faddp has latency/throughput that
+        // matches fadd instruction and hence, every faddp instruction can be
+        // considered to have a relative cost=1 with
+        // CostKind=TCK_RecipThroughput.
+        return (LT.first - 1) + /*No of faddp instructions*/ Log2_32(NElts);
+      }
+    }
+  } break;
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davemgreen wrote:

You could remove this set of brackets I believe - they should only be needed in switches if there is a variable defined inside them, and the if(isVector()) protects against that.

https://github.com/llvm/llvm-project/pull/108791