[llvm] [AMDGPU][NewPM] Port SILowerSGPRSpills to NPM (PR #108934)
Akshat Oke via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 19 06:10:01 PDT 2024
https://github.com/Akshat-Oke updated https://github.com/llvm/llvm-project/pull/108934
>From e78b49bc03c510247b559ae0fd0095adca32f019 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Tue, 17 Sep 2024 06:00:43 +0000
Subject: [PATCH 1/2] [AMDGPU][NewPM] Port SILowerSGPRSpills to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 4 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 +--
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 50 +++++++++++++------
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 29 +++++++++++
.../sgpr-spill-dead-frame-in-dbg-value.mir | 1 +
...fi-skip-processing-stack-arg-dbg-value.mir | 1 +
llvm/test/CodeGen/AMDGPU/spill192.mir | 2 +
8 files changed, 75 insertions(+), 20 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 07f9bbeb42029b..b2dd354e496a2e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -187,8 +187,8 @@ extern char &AMDGPUGlobalISelDivergenceLoweringID;
void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &);
extern char &AMDGPUMarkLastScratchLoadID;
-void initializeSILowerSGPRSpillsPass(PassRegistry &);
-extern char &SILowerSGPRSpillsID;
+void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
+extern char &SILowerSGPRSpillsLegacyID;
void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
extern char &SILoadStoreOptimizerLegacyID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 97661bf9837f92..99707c2f22526b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -102,4 +102,5 @@ MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
+MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index f860b139945122..d0de7b9c1b6476 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -37,6 +37,7 @@
#include "SIFixSGPRCopies.h"
#include "SIFoldOperands.h"
#include "SILoadStoreOptimizer.h"
+#include "SILowerSGPRSpills.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIPeepholeSDWA.h"
@@ -412,7 +413,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR);
initializeSILowerWWMCopiesPass(*PR);
initializeAMDGPUMarkLastScratchLoadPass(*PR);
- initializeSILowerSGPRSpillsPass(*PR);
+ initializeSILowerSGPRSpillsLegacyPass(*PR);
initializeSIFixSGPRCopiesLegacyPass(*PR);
initializeSIFixVGPRCopiesPass(*PR);
initializeSIFoldOperandsLegacyPass(*PR);
@@ -1440,7 +1441,7 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
addPass(createSGPRAllocPass(false));
// Equivalent of PEI for SGPRs.
- addPass(&SILowerSGPRSpillsID);
+ addPass(&SILowerSGPRSpillsLegacyID);
addPass(&SIPreAllocateWWMRegsID);
addPass(createVGPRAllocPass(false));
@@ -1464,7 +1465,7 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(createVirtRegRewriter(false));
// Equivalent of PEI for SGPRs.
- addPass(&SILowerSGPRSpillsID);
+ addPass(&SILowerSGPRSpillsLegacyID);
addPass(&SIPreAllocateWWMRegsID);
addPass(createVGPRAllocPass(true));
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index a32a18e506018b..28bba8cfd73528 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -15,6 +15,7 @@
//
//===----------------------------------------------------------------------===//
+#include "SILowerSGPRSpills.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -32,7 +33,7 @@ using MBBVector = SmallVector<MachineBasicBlock *, 4>;
namespace {
-class SILowerSGPRSpills : public MachineFunctionPass {
+class SILowerSGPRSpills {
private:
const SIRegisterInfo *TRI = nullptr;
const SIInstrInfo *TII = nullptr;
@@ -45,14 +46,20 @@ class SILowerSGPRSpills : public MachineFunctionPass {
MBBVector RestoreBlocks;
public:
- static char ID;
-
- SILowerSGPRSpills() : MachineFunctionPass(ID) {}
-
+ SILowerSGPRSpills(LiveIntervals *LIS, SlotIndexes *Indexes)
+ : LIS(LIS), Indexes(Indexes) {}
+ bool run(MachineFunction &MF);
void calculateSaveRestoreBlocks(MachineFunction &MF);
bool spillCalleeSavedRegs(MachineFunction &MF,
SmallVectorImpl<int> &CalleeSavedFIs);
void extendWWMVirtRegLiveness(MachineFunction &MF, LiveIntervals *LIS);
+};
+
+class SILowerSGPRSpillsLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ SILowerSGPRSpillsLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -71,16 +78,16 @@ class SILowerSGPRSpills : public MachineFunctionPass {
} // end anonymous namespace
-char SILowerSGPRSpills::ID = 0;
+char SILowerSGPRSpillsLegacy::ID = 0;
-INITIALIZE_PASS_BEGIN(SILowerSGPRSpills, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
"SI lower SGPR spill instructions", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
-INITIALIZE_PASS_END(SILowerSGPRSpills, DEBUG_TYPE,
+INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
"SI lower SGPR spill instructions", false, false)
-char &llvm::SILowerSGPRSpillsID = SILowerSGPRSpills::ID;
+char &llvm::SILowerSGPRSpillsLegacyID = SILowerSGPRSpillsLegacy::ID;
/// Insert spill code for the callee-saved registers used in the function.
static void insertCSRSaves(MachineBasicBlock &SaveBlock,
@@ -306,16 +313,19 @@ void SILowerSGPRSpills::extendWWMVirtRegLiveness(MachineFunction &MF,
}
}
-bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
+bool SILowerSGPRSpillsLegacy::runOnMachineFunction(MachineFunction &MF) {
+ auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ LiveIntervals *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
+ auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
+ SlotIndexes *Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
+ return SILowerSGPRSpills(LIS, Indexes).run(MF);
+}
+
+bool SILowerSGPRSpills::run(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
TII = ST.getInstrInfo();
TRI = &TII->getRegisterInfo();
- auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
- LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
- auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
- Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
-
assert(SaveBlocks.empty() && RestoreBlocks.empty());
// First, expose any CSR SGPR spills. This is mostly the same as what PEI
@@ -446,3 +456,13 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
return MadeChange;
}
+
+PreservedAnalyses
+SILowerSGPRSpillsPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+ auto *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF);
+ auto *Indexes = MFAM.getCachedResult<SlotIndexesAnalysis>(MF);
+ SILowerSGPRSpills(LIS, Indexes).run(MF);
+ return PreservedAnalyses::all();
+}
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
new file mode 100644
index 00000000000000..730b3f8c617bd3
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
@@ -0,0 +1,29 @@
+//===- SILowerSGPRSpills.h --------------------------------------*- C++- *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SILOWERSGPRSPILLS_H
+#define LLVM_LIB_TARGET_AMDGPU_SILOWERSGPRSPILLS_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+class SILowerSGPRSpillsPass : public PassInfoMixin<SILowerSGPRSpillsPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getClearedProperties() {
+ // SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
+ return MachineFunctionProperties()
+ .set(MachineFunctionProperties::Property::IsSSA)
+ .set(MachineFunctionProperties::Property::NoVRegs);
+ }
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_SILOWERSGPRSPILLS_H
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
index a7c841d54f7c97..189aead1e5646a 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
@@ -1,5 +1,6 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILL %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck -check-prefix=PEI %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -passes=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILL %s
# After handling the SGPR spill to VGPR in SILowerSGPRSpills pass, replace the dead frame index in the DBG_VALUE instruction with reg 0.
# Otherwise, the test would crash during PEI while trying to replace the dead frame index.
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
index a6cb7d4af7641c..6238c46edd6d14 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -passes=si-lower-sgpr-spills -o - %s | FileCheck %s
# After handling the SGPR spill to VGPR in SILowerSGPRSpills pass, we replace the dead frame index in the DBG_VALUE instruction with reg 0.
# Skip looking for frame indices in the debug value instruction for incoming arguments passed via stack. The test would crash otherwise.
diff --git a/llvm/test/CodeGen/AMDGPU/spill192.mir b/llvm/test/CodeGen/AMDGPU/spill192.mir
index 42c792b1538ae7..5040140a3e9351 100644
--- a/llvm/test/CodeGen/AMDGPU/spill192.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill192.mir
@@ -3,6 +3,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
+# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
+
# Make sure spill/restore of 192 bit registers works. We have to
# settle for a MIR test for now since inlineasm fails without 192-bit
# MVT.
>From d6b8344f0fd2cf1cc6886b3c138cdac94ef87864 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 19 Sep 2024 13:09:30 +0000
Subject: [PATCH 2/2] Sort registry declarations
---
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 99707c2f22526b..0ebf34c901c142 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -100,7 +100,7 @@ MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
+MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
-MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
#undef MACHINE_FUNCTION_PASS
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