[llvm] [Analysis] Teach isDereferenceableAndAlignedInLoop about SCEV predicates (PR #106562)

[David Sherwood via llvm-commits]

david-arm wrote:

I've rebased the PR and also updated some code in LoopVectorizationLegality to also pass the predicates into isDereferenceableReadOnlyLoop, which adds support for more early exit loops being vectorised.

https://github.com/llvm/llvm-project/pull/106562