[llvm] [AMDGPU] Add hazard workarounds to insertIndirectBranch (PR #109127)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 19 02:47:29 PDT 2024
jayfoad wrote:
> > In principle we could pad the size of every instruction with the worst case number of instructions required for hazards getInstSizeInBytes
>
> This doesn't really seem great. Maybe I am misunderstanding, but if we assume that every instruction could require zero or one workaround instruction, then that halves the effective direct branch distance? We must also account for `s_delay_alu` instructions which are added before relaxation at present, so that's another 4 bytes? Now branch distance is reduced by 3x.
>
> I think the solution in this patch works fine for now. If we run into this again then I think the hazard mitigation infrastructure should be refactored to allow access to it outside the post RA scheduler, so `insertIndirectBranch` and similar could call into the hazard mitigation after inserting instructions.
Agreed - I think it would be a mistake to move branch relaxation earlier.
https://github.com/llvm/llvm-project/pull/109127
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