[llvm] [llvm][ARM][CodeGen] Disable MEMCPY LDM/STM inlining for Cortex v7-m (PR #106378)

[Nashe Mncube via llvm-commits]

nasherm wrote:

> It looks like later codegen passes opportunistically form ldrd/strd and ldm/stm, depending on the input values; do we want that? 

I believe  this is the intended behavior as this causes the best performance improvements. Switching to purely using plain load/stores doesn't provide the same performance improvement.

https://github.com/llvm/llvm-project/pull/106378