[llvm] [llvm][ARM][CodeGen] Disable MEMCPY LDM/STM inlining for Cortex v7-m (PR #106378)

[Nashe Mncube via llvm-commits]

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@@ -192,6 +302,12 @@ SDValue ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(
     return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size,
                                   Alignment.value(), RTLIB::MEMCPY);
 
+  if (Subtarget.isCortexM7() &&
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nasherm wrote:

> I've opted by just using a boolean check for terseness. Do let me know if you'd prefer an ST feature
I see that this causes failures since it triggers the optimisation for other cores. So I'll go for your original suggestion

https://github.com/llvm/llvm-project/pull/106378