[llvm] 1a793a8 - [LLVM][TableGen] Change X86InstrMapping to use const RecordKeeper (#109066)

[via llvm-commits]

Author: Rahul Joshi
Date: 2024-09-18T10:41:21-07:00
New Revision: 1a793a8ca024a5b6e6a659cc4e1a8c4ab45e3cee

URL: https://github.com/llvm/llvm-project/commit/1a793a8ca024a5b6e6a659cc4e1a8c4ab45e3cee
DIFF: https://github.com/llvm/llvm-project/commit/1a793a8ca024a5b6e6a659cc4e1a8c4ab45e3cee.diff

LOG: [LLVM][TableGen] Change X86InstrMapping to use const RecordKeeper (#109066)

Change X86InstrMappingEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

Added: 
    

Modified: 
    llvm/utils/TableGen/X86InstrMappingEmitter.cpp
    llvm/utils/TableGen/X86RecognizableInstr.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 0abe353a9a579b..f68c727cbe9230 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -26,8 +26,8 @@ using namespace X86Disassembler;
 namespace {
 
 class X86InstrMappingEmitter {
-  RecordKeeper &Records;
-  CodeGenTarget Target;
+  const RecordKeeper &Records;
+  const CodeGenTarget Target;
 
   // Hold all pontentially compressible EVEX instructions
   std::vector<const CodeGenInstruction *> PreCompressionInsts;
@@ -44,7 +44,7 @@ class X86InstrMappingEmitter {
   PredicateInstMap PredicateInsts;
 
 public:
-  X86InstrMappingEmitter(RecordKeeper &R) : Records(R), Target(R) {}
+  X86InstrMappingEmitter(const RecordKeeper &R) : Records(R), Target(R) {}
 
   // run - Output X86 EVEX compression tables.
   void run(raw_ostream &OS);
@@ -63,8 +63,8 @@ class X86InstrMappingEmitter {
   void printClassDef(raw_ostream &OS);
   // Prints the given table as a C++ array of type X86TableEntry under the guard
   // \p Macro.
-  void printTable(const std::vector<Entry> &Table, StringRef Name,
-                  StringRef Macro, raw_ostream &OS);
+  void printTable(ArrayRef<Entry> Table, StringRef Name, StringRef Macro,
+                  raw_ostream &OS);
 };
 
 void X86InstrMappingEmitter::printClassDef(raw_ostream &OS) {
@@ -90,9 +90,8 @@ static void printMacroEnd(StringRef Macro, raw_ostream &OS) {
   OS << "#endif // " << Macro << "\n\n";
 }
 
-void X86InstrMappingEmitter::printTable(const std::vector<Entry> &Table,
-                                        StringRef Name, StringRef Macro,
-                                        raw_ostream &OS) {
+void X86InstrMappingEmitter::printTable(ArrayRef<Entry> Table, StringRef Name,
+                                        StringRef Macro, raw_ostream &OS) {
   printMacroBegin(Macro, OS);
 
   OS << "static const X86TableEntry " << Name << "[] = {\n";
@@ -220,7 +219,7 @@ void X86InstrMappingEmitter::emitCompressEVEXTable(
       assert(NewRec && "Instruction not found!");
       NewInst = &Target.getInstruction(NewRec);
     } else if (Name.ends_with("_EVEX")) {
-      if (auto *NewRec = Records.getDef(Name.drop_back(5)))
+      if (const auto *NewRec = Records.getDef(Name.drop_back(5)))
         NewInst = &Target.getInstruction(NewRec);
     } else if (Name.ends_with("_ND"))
       // Leave it to ND2NONND table.
@@ -319,7 +318,7 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
     if (!isInteresting(Rec) || NoCompressSet.find(Name) != NoCompressSet.end())
       continue;
     if (ManualMap.find(Name) != ManualMap.end()) {
-      auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
+      const auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
       assert(NewRec && "Instruction not found!");
       auto &NewInst = Target.getInstruction(NewRec);
       Table.push_back(std::pair(Inst, &NewInst));
@@ -328,10 +327,10 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
 
     if (!Name.ends_with("_ND"))
       continue;
-    auto *NewRec = Records.getDef(Name.drop_back(3));
+    const auto *NewRec = Records.getDef(Name.drop_back(3));
     if (!NewRec)
       continue;
-    auto &NewInst = Target.getInstruction(NewRec);
+    const auto &NewInst = Target.getInstruction(NewRec);
     if (isRegisterOperand(NewInst.Operands[0].Rec))
       Table.push_back(std::pair(Inst, &NewInst));
   }
@@ -353,15 +352,15 @@ void X86InstrMappingEmitter::emitSSE2AVXTable(
     if (!isInteresting(Rec))
       continue;
     if (ManualMap.find(Name) != ManualMap.end()) {
-      auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
+      const auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
       assert(NewRec && "Instruction not found!");
-      auto &NewInst = Target.getInstruction(NewRec);
+      const auto &NewInst = Target.getInstruction(NewRec);
       Table.push_back(std::pair(Inst, &NewInst));
       continue;
     }
 
     std::string NewName = ("V" + Name).str();
-    auto *AVXRec = Records.getDef(NewName);
+    const auto *AVXRec = Records.getDef(NewName);
     if (!AVXRec)
       continue;
     auto &AVXInst = Target.getInstruction(AVXRec);

diff  --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index a1e67e3ea692a3..4386e8361712b8 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -154,14 +154,13 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
       UID(uid), Spec(&tables.specForUID(uid)) {
   // Check for 64-bit inst which does not require REX
   // FIXME: Is there some better way to check for In64BitMode?
-  std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates");
-  for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
-    if (Predicates[i]->getName().contains("Not64Bit") ||
-        Predicates[i]->getName().contains("In32Bit")) {
+  for (const Record *Predicate : Rec->getValueAsListOfConstDefs("Predicates")) {
+    if (Predicate->getName().contains("Not64Bit") ||
+        Predicate->getName().contains("In32Bit")) {
       Is32Bit = true;
       break;
     }
-    if (Predicates[i]->getName().contains("In64Bit")) {
+    if (Predicate->getName().contains("In64Bit")) {
       Is64Bit = true;
       break;
     }