[llvm] [AMDGPU] Create an AMDGPUIfConverter pass (PR #106415)

[Jay Foad via llvm-commits]

Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>,
Juan Manuel Martinez =?utf-8?q?Caamaño?= <juamarti at amd.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/106415 at github.com>


jayfoad wrote:

> @jayfoad An extract of the motivating example is this code: https://godbolt.org/z/dPdf7r381 .
```
        s_cmp_lt_i32 s0, 1
        s_cbranch_scc1 .LBB0_2
        s_clause 0x1
        s_load_dwordx2 s[6:7], s[4:5], 0x0
        s_load_dwordx4 s[0:3], s[4:5], 0x10
        s_waitcnt lgkmcnt(0)
        s_load_dword s6, s[6:7], 0x0
        s_load_dword s4, s[4:5], 0x20
        s_waitcnt lgkmcnt(0)
        v_mov_b32_e32 v0, s6
        v_mov_b32_e32 v1, s4
        buffer_store_dword v0, v1, s[0:3], 0 offen
.LBB0_2:
```
So you want to remove the `s_cbranch_scc1` and instead rely on setting EXEC to 0, even though the branch condition is uniform? Is that really viable, given that the s_load instructions can't be predicated with EXEC? What codegen would you like to see for this example?

https://github.com/llvm/llvm-project/pull/106415