[llvm] [NFC] Update function names in MCTargetAsmParser.h (PR #108643)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 18 08:43:15 PDT 2024
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/108643
>From 8894acfde0bac142926febea730c28fde9c1491f Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 13 Sep 2024 20:38:55 +0000
Subject: [PATCH 1/4] [NFC] Update function names in MCTargetAsmParser.h
Update function names to adhere to LLVM coding standard.
---
.../llvm/MC/MCParser/MCTargetAsmParser.h | 14 +-
llvm/lib/MC/MCParser/AsmParser.cpp | 6 +-
llvm/lib/MC/MCParser/MCTargetAsmParser.cpp | 6 +-
llvm/lib/MC/MCParser/MasmParser.cpp | 6 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp | 16 +--
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 14 +-
.../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 16 +--
.../lib/Target/AVR/AsmParser/AVRAsmParser.cpp | 8 +-
.../lib/Target/BPF/AsmParser/BPFAsmParser.cpp | 10 +-
.../Hexagon/AsmParser/HexagonAsmParser.cpp | 16 +--
.../Target/Lanai/AsmParser/LanaiAsmParser.cpp | 8 +-
.../AsmParser/LoongArchAsmParser.cpp | 10 +-
.../MSP430/AsmParser/MSP430AsmParser.cpp | 8 +-
.../Target/Mips/AsmParser/MipsAsmParser.cpp | 14 +-
.../Target/PowerPC/AsmParser/PPCAsmParser.cpp | 124 +++++++++---------
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 14 +-
.../Target/Sparc/AsmParser/SparcAsmParser.cpp | 10 +-
.../SystemZ/AsmParser/SystemZAsmParser.cpp | 8 +-
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp | 8 +-
.../AsmParser/WebAssemblyAsmParser.cpp | 4 +-
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 16 +--
21 files changed, 168 insertions(+), 168 deletions(-)
diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
index 49ce417e6fbb20..93e27a02aeffcb 100644
--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
@@ -439,14 +439,14 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// \param Operands [out] - The list of parsed operands, this returns
/// ownership of them to the caller.
/// \return True on failure.
- virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ virtual bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) = 0;
- virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ virtual bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
AsmToken Token, OperandVector &Operands) {
- return ParseInstruction(Info, Name, Token.getLoc(), Operands);
+ return parseInstruction(Info, Name, Token.getLoc(), Operands);
}
- /// ParseDirective - Parse a target specific assembler directive
+ /// parseDirectives - Parse a target specific assembler directive
/// This method is deprecated, use 'parseDirective' instead.
///
/// The parser is positioned following the directive name. The target
@@ -457,7 +457,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// end-of-statement token and false is returned.
///
/// \param DirectiveID - the identifier token of the directive.
- virtual bool ParseDirective(AsmToken DirectiveID) { return true; }
+ virtual bool parseDirectives(AsmToken DirectiveID) { return true; }
/// Parses a target-specific assembler directive.
///
@@ -477,13 +477,13 @@ class MCTargetAsmParser : public MCAsmParserExtension {
///
/// On failure, the target parser is responsible for emitting a diagnostic
/// explaining the match failure.
- virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ virtual bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) = 0;
/// Allows targets to let registers opt out of clobber lists.
- virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
+ virtual bool omitRegisterFromClobberLists(unsigned RegNo) { return false; }
/// Allow a target to add special case operand matching for things that
/// tblgen doesn't/can't handle effectively. For example, literal
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index 66e52fe2d08f8d..9eff35642c9f39 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -2322,7 +2322,7 @@ bool AsmParser::parseAndMatchAndEmitTargetInstruction(ParseStatementInfo &Info,
// Canonicalize the opcode to lower case.
std::string OpcodeStr = IDVal.lower();
ParseInstructionInfo IInfo(Info.AsmRewrites);
- bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
+ bool ParseHadError = getTargetParser().parseInstruction(IInfo, OpcodeStr, ID,
Info.ParsedOperands);
Info.ParseError = ParseHadError;
@@ -2379,7 +2379,7 @@ bool AsmParser::parseAndMatchAndEmitTargetInstruction(ParseStatementInfo &Info,
// If parsing succeeded, match the instruction.
if (!ParseHadError) {
uint64_t ErrorInfo;
- if (getTargetParser().MatchAndEmitInstruction(
+ if (getTargetParser().matchAndEmitInstruction(
IDLoc, Info.Opcode, Info.ParsedOperands, Out, ErrorInfo,
getTargetParser().isParsingMSInlineAsm()))
return true;
@@ -6029,7 +6029,7 @@ bool AsmParser::parseMSInlineAsm(
// Register operand.
if (Operand.isReg() && !Operand.needAddressOf() &&
- !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
+ !getTargetParser().omitRegisterFromClobberLists(Operand.getReg())) {
unsigned NumDefs = Desc.getNumDefs();
// Clobber.
if (NumDefs && Operand.getMCOperandNum() < NumDefs)
diff --git a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
index 665d92eb9a21c5..931d5888c9034c 100644
--- a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
@@ -31,15 +31,15 @@ const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
ParseStatus MCTargetAsmParser::parseDirective(AsmToken DirectiveID) {
SMLoc StartTokLoc = getTok().getLoc();
- // Delegate to ParseDirective by default for transition period. Once the
+ // Delegate to parseDirectives by default for transition period. Once the
// transition is over, this method should just return NoMatch.
- bool Res = ParseDirective(DirectiveID);
+ bool Res = parseDirectives(DirectiveID);
// Some targets erroneously report success after emitting an error.
if (getParser().hasPendingError())
return ParseStatus::Failure;
- // ParseDirective returns true if there was an error or if the directive is
+ // parseDirectives returns true if there was an error or if the directive is
// not target-specific. Disambiguate the two cases by comparing position of
// the lexer before and after calling the method: if no tokens were consumed,
// there was no match, otherwise there was a failure.
diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp
index 9f619c5018b509..0c64af9e460ea0 100644
--- a/llvm/lib/MC/MCParser/MasmParser.cpp
+++ b/llvm/lib/MC/MCParser/MasmParser.cpp
@@ -2657,7 +2657,7 @@ bool MasmParser::parseStatement(ParseStatementInfo &Info,
// Canonicalize the opcode to lower case.
std::string OpcodeStr = IDVal.lower();
ParseInstructionInfo IInfo(Info.AsmRewrites);
- bool ParseHadError = getTargetParser().ParseInstruction(IInfo, OpcodeStr, ID,
+ bool ParseHadError = getTargetParser().parseInstruction(IInfo, OpcodeStr, ID,
Info.ParsedOperands);
Info.ParseError = ParseHadError;
@@ -2714,7 +2714,7 @@ bool MasmParser::parseStatement(ParseStatementInfo &Info,
// If parsing succeeded, match the instruction.
if (!ParseHadError) {
uint64_t ErrorInfo;
- if (getTargetParser().MatchAndEmitInstruction(
+ if (getTargetParser().matchAndEmitInstruction(
IDLoc, Info.Opcode, Info.ParsedOperands, Out, ErrorInfo,
getTargetParser().isParsingMSInlineAsm()))
return true;
@@ -7389,7 +7389,7 @@ bool MasmParser::parseMSInlineAsm(
// Register operand.
if (Operand.isReg() && !Operand.needAddressOf() &&
- !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
+ !getTargetParser().omitRegisterFromClobberLists(Operand.getReg())) {
unsigned NumDefs = Desc.getNumDefs();
// Clobber.
if (NumDefs && Operand.getMCOperandNum() < NumDefs)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 13a7eef4788524..72c51f5ab09a61 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -231,7 +231,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
SmallVectorImpl<SMLoc> &Loc);
unsigned getNumRegsForRegKind(RegKind K);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -321,12 +321,12 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool areEqualRegs(const MCParsedAsmOperand &Op1,
const MCParsedAsmOperand &Op2) const override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -5086,9 +5086,9 @@ bool AArch64AsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
return false;
}
-/// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its
+/// parseInstruction - Parse an AArch64 instruction mnemonic followed by its
/// operands.
-bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
Name = StringSwitch<StringRef>(Name.lower())
@@ -6205,7 +6205,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
static const char *getSubtargetFeatureName(uint64_t Val);
-bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -6798,8 +6798,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// ParseDirective parses the arm specific directives
-bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
+/// parseDirectives parses the arm specific directives
+bool AArch64AsmParser::parseDirectives(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
bool IsCOFF = Format == MCContext::IsCOFF;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 5db6c52d189e37..51de0f8ffb12d9 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1256,7 +1256,7 @@ class KernelScopeInfo {
}
void usesAgprAt(int i) {
- // Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction
+ // Instruction will error in AMDGPUAsmParser::matchAndEmitInstruction
if (!hasMAIInsts(*MSTI))
return;
@@ -1597,15 +1597,15 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
OperandMode Mode = OperandMode_Default);
StringRef parseMnemonicSuffix(StringRef Name);
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
//bool ProcessInstruction(MCInst &Inst);
@@ -5288,7 +5288,7 @@ static bool isInvalidVOPDY(const OperandVector &Operands,
return false;
}
-bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool AMDGPUAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -6194,7 +6194,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
return false;
}
-bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool AMDGPUAsmParser::parseDirectives(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getString();
if (isHsaAbi(getSTI())) {
@@ -6393,7 +6393,7 @@ static void applyMnemonicAliases(StringRef &Mnemonic,
const FeatureBitset &Features,
unsigned VariantID);
-bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool AMDGPUAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
// Add the instruction mnemonic
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 3e3f134d347016..64e4dae5365085 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -712,9 +712,9 @@ class ARMAsmParser : public MCTargetAsmParser {
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -723,7 +723,7 @@ class ARMAsmParser : public MCTargetAsmParser {
checkEarlyTargetMatchPredicate(MCInst &Inst,
const OperandVector &Operands) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -7051,7 +7051,7 @@ void removeVPTCondCode(OperandVector &Operands, unsigned &MnemonicOpsEndInd) {
}
/// Parse an arm instruction mnemonic followed by its operands.
-bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool ARMAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
MCAsmParser &Parser = getParser();
@@ -11350,7 +11350,7 @@ static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
unsigned VariantID = 0);
static const char *getSubtargetFeatureName(uint64_t Val);
-bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool ARMAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -11427,8 +11427,8 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// parseDirective parses the arm specific directives
-bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
+/// parseDirectives parses the arm specific directives
+bool ARMAsmParser::parseDirectives(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
bool IsCOFF = Format == MCContext::IsCOFF;
@@ -12120,7 +12120,7 @@ bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
return false;
}
-/// parseDirective
+/// parseDirectivePad
/// ::= .pad offset
bool ARMAsmParser::parseDirectivePad(SMLoc L) {
MCAsmParser &Parser = getParser();
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
index 193722fa356114..b4971e43b48ebf 100644
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
@@ -51,7 +51,7 @@ class AVRAsmParser : public MCTargetAsmParser {
#define GET_ASSEMBLER_HEADER
#include "AVRGenAsmMatcher.inc"
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -60,7 +60,7 @@ class AVRAsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
@@ -320,7 +320,7 @@ bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
return false;
}
-bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
+bool AVRAsmParser::matchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -623,7 +623,7 @@ void AVRAsmParser::eatComma() {
}
}
-bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool AVRAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Mnemonic, SMLoc NameLoc,
OperandVector &Operands) {
Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
index 9672ed009e9be1..98ab0f2bd399b5 100644
--- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
+++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
@@ -34,7 +34,7 @@ class BPFAsmParser : public MCTargetAsmParser {
bool PreMatchCheck(OperandVector &Operands);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -43,7 +43,7 @@ class BPFAsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
// "=" is used as assignment operator for assembly statment, so can't be used
@@ -304,7 +304,7 @@ bool BPFAsmParser::PreMatchCheck(OperandVector &Operands) {
return false;
}
-bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool BPFAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -483,9 +483,9 @@ ParseStatus BPFAsmParser::parseImmediate(OperandVector &Operands) {
return ParseStatus::Success;
}
-/// ParseInstruction - Parse an BPF instruction which is in BPF verifier
+/// parseInstruction - Parse an BPF instruction which is in BPF verifier
/// format.
-bool BPFAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool BPFAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
// The first operand could be either register or actually an operator.
unsigned RegNo = MatchRegisterName(Name);
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index 2fb1c484fc8a14..74616fa7da1ead 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -134,7 +134,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
OperandVector &InstOperands, uint64_t &ErrorInfo,
bool MatchingInlineAsm);
void eatToEndOfPacket();
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -180,15 +180,15 @@ class HexagonAsmParser : public MCTargetAsmParser {
bool parseExpressionOrOperand(OperandVector &Operands);
bool parseExpression(MCExpr const *&Expr);
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override {
llvm_unreachable("Unimplemented");
}
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
OperandVector &Operands) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
};
/// HexagonOperand - Instances of this class represent a parsed Hexagon machine
@@ -614,7 +614,7 @@ void HexagonAsmParser::eatToEndOfPacket() {
InBrackets = false;
}
-bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool HexagonAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -710,8 +710,8 @@ bool HexagonAsmParser::parseDirectiveAttribute(SMLoc L) {
return false;
}
-/// ParseDirective parses the Hexagon specific directives
-bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
+/// parseDirectives parses the Hexagon specific directives
+bool HexagonAsmParser::parseDirectives(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal.lower() == ".falign")
return ParseDirectiveFalign(256, DirectiveID.getLoc());
@@ -1278,7 +1278,7 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
}
}
-bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool HexagonAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, AsmToken ID,
OperandVector &Operands) {
getLexer().UnLex(ID);
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
index 6ab1375b974ec6..280f1f3ddbb69f 100644
--- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
+++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
@@ -62,14 +62,14 @@ class LanaiAsmParser : public MCTargetAsmParser {
bool parsePrePost(StringRef Type, int *OffsetValue);
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -645,7 +645,7 @@ struct LanaiOperand : public MCParsedAsmOperand {
} // end anonymous namespace
-bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
+bool LanaiAsmParser::matchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -1161,7 +1161,7 @@ static bool MaybePredicatedInst(const OperandVector &Operands) {
.Default(false);
}
-bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo & /*Info*/,
+bool LanaiAsmParser::parseInstruction(ParseInstructionInfo & /*Info*/,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// First operand is token for instruction
diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
index b8f1cdfd2cb354..57c42024b4d2b2 100644
--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
@@ -47,10 +47,10 @@ class LoongArchAsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -65,7 +65,7 @@ class LoongArchAsmParser : public MCTargetAsmParser {
const Twine &Msg);
/// Helper for processing MC instructions that have been successfully matched
- /// by MatchAndEmitInstruction.
+ /// by matchAndEmitInstruction.
bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
MCStreamer &Out);
@@ -793,7 +793,7 @@ bool LoongArchAsmParser::parseOperand(OperandVector &Operands,
return Error(getLoc(), "unknown operand");
}
-bool LoongArchAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool LoongArchAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// First operand in MCInst is instruction mnemonic.
@@ -1506,7 +1506,7 @@ bool LoongArchAsmParser::generateImmOutOfRangeError(
return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
}
-bool LoongArchAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool LoongArchAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
index 2bc1a89ef59cf0..34ae80669f2c3c 100644
--- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
+++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
@@ -40,7 +40,7 @@ class MSP430AsmParser : public MCTargetAsmParser {
MCAsmParser &Parser;
const MCRegisterInfo *MRI;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -49,7 +49,7 @@ class MSP430AsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
@@ -252,7 +252,7 @@ class MSP430Operand : public MCParsedAsmOperand {
};
} // end anonymous namespace
-bool MSP430AsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
+bool MSP430AsmParser::matchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -385,7 +385,7 @@ bool MSP430AsmParser::parseJccInstruction(ParseInstructionInfo &Info,
return false;
}
-bool MSP430AsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool MSP430AsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// Drop .w suffix
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8ab435c6c6fd18..91390ce028d17e 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -174,7 +174,7 @@ class MipsAsmParser : public MCTargetAsmParser {
const OperandVector &Operands) override;
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -190,10 +190,10 @@ class MipsAsmParser : public MCTargetAsmParser {
bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
ParseStatus parseMemOperand(OperandVector &Operands);
ParseStatus matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
@@ -5992,7 +5992,7 @@ static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands,
return Loc;
}
-bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool MipsAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -6997,10 +6997,10 @@ bool MipsAsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
return Op1.getReg() == Op2.getReg();
}
-bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool MipsAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
MCAsmParser &Parser = getParser();
- LLVM_DEBUG(dbgs() << "ParseInstruction\n");
+ LLVM_DEBUG(dbgs() << "parseInstruction\n");
// We have reached first instruction, module directive are now forbidden.
getTargetStreamer().forbidModuleDirective();
@@ -8630,7 +8630,7 @@ bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
return false;
}
-bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
+bool MipsAsmParser::parseDirectives(AsmToken DirectiveID) {
// This returns false if this function recognizes the directive
// regardless of whether it is successfully handles or reports an
// error. Otherwise it returns true to give the generic parser a
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 59ad995b44b04a..8a369154d5371f 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -103,32 +103,32 @@ class PPCAsmParser : public MCTargetAsmParser {
bool isPPC64() const { return IsPPC64; }
- bool MatchRegisterName(MCRegister &RegNo, int64_t &IntVal);
+ bool matchRegisterName(MCRegister &RegNo, int64_t &IntVal);
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
+ const MCExpr *extractModifierFromExpr(const MCExpr *E,
PPCMCExpr::VariantKind &Variant);
- const MCExpr *FixupVariantKind(const MCExpr *E);
- bool ParseExpression(const MCExpr *&EVal);
+ const MCExpr *fixupVariantKind(const MCExpr *E);
+ bool parseExpression(const MCExpr *&EVal);
- bool ParseOperand(OperandVector &Operands);
+ bool parseOperand(OperandVector &Operands);
- bool ParseDirectiveWord(unsigned Size, AsmToken ID);
- bool ParseDirectiveTC(unsigned Size, AsmToken ID);
- bool ParseDirectiveMachine(SMLoc L);
- bool ParseDirectiveAbiVersion(SMLoc L);
- bool ParseDirectiveLocalEntry(SMLoc L);
- bool ParseGNUAttribute(SMLoc L);
+ bool parseDirectiveWord(unsigned Size, AsmToken ID);
+ bool parseDirectiveTC(unsigned Size, AsmToken ID);
+ bool parseDirectiveMachine(SMLoc L);
+ bool parseDirectiveAbiVersion(SMLoc L);
+ bool parseDirectiveLocalEntry(SMLoc L);
+ bool parseGNUAttribute(SMLoc L);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
+ void processInstruction(MCInst &Inst, const OperandVector &Ops);
/// @name Auto-generated Match Functions
/// {
@@ -150,10 +150,10 @@ class PPCAsmParser : public MCTargetAsmParser {
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -818,7 +818,7 @@ addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
}
-void PPCAsmParser::ProcessInstruction(MCInst &Inst,
+void PPCAsmParser::processInstruction(MCInst &Inst,
const OperandVector &Operands) {
int Opcode = Inst.getOpcode();
switch (Opcode) {
@@ -1252,7 +1252,7 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
unsigned VariantID = 0);
-bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool PPCAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -1261,7 +1261,7 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
case Match_Success:
// Post-process instructions (typically extended mnemonics)
- ProcessInstruction(Inst, Operands);
+ processInstruction(Inst, Operands);
Inst.setLoc(IDLoc);
Out.emitInstruction(Inst, getSTI());
return false;
@@ -1291,7 +1291,7 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-bool PPCAsmParser::MatchRegisterName(MCRegister &RegNo, int64_t &IntVal) {
+bool PPCAsmParser::matchRegisterName(MCRegister &RegNo, int64_t &IntVal) {
if (getParser().getTok().is(AsmToken::Percent))
getParser().Lex(); // Eat the '%'.
@@ -1364,7 +1364,7 @@ ParseStatus PPCAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
EndLoc = Tok.getEndLoc();
Reg = PPC::NoRegister;
int64_t IntVal;
- if (MatchRegisterName(Reg, IntVal))
+ if (matchRegisterName(Reg, IntVal))
return ParseStatus::NoMatch;
return ParseStatus::Success;
}
@@ -1376,7 +1376,7 @@ ParseStatus PPCAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
/// and a modified expression using the default symbol variant.
/// Otherwise, return NULL.
const MCExpr *PPCAsmParser::
-ExtractModifierFromExpr(const MCExpr *E,
+extractModifierFromExpr(const MCExpr *E,
PPCMCExpr::VariantKind &Variant) {
MCContext &Context = getParser().getContext();
Variant = PPCMCExpr::VK_PPC_None;
@@ -1426,7 +1426,7 @@ ExtractModifierFromExpr(const MCExpr *E,
case MCExpr::Unary: {
const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
- const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
+ const MCExpr *Sub = extractModifierFromExpr(UE->getSubExpr(), Variant);
if (!Sub)
return nullptr;
return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
@@ -1435,8 +1435,8 @@ ExtractModifierFromExpr(const MCExpr *E,
case MCExpr::Binary: {
const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
PPCMCExpr::VariantKind LHSVariant, RHSVariant;
- const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
- const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
+ const MCExpr *LHS = extractModifierFromExpr(BE->getLHS(), LHSVariant);
+ const MCExpr *RHS = extractModifierFromExpr(BE->getRHS(), RHSVariant);
if (!LHS && !RHS)
return nullptr;
@@ -1465,7 +1465,7 @@ ExtractModifierFromExpr(const MCExpr *E,
/// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
/// FIXME: This is a hack.
const MCExpr *PPCAsmParser::
-FixupVariantKind(const MCExpr *E) {
+fixupVariantKind(const MCExpr *E) {
MCContext &Context = getParser().getContext();
switch (E->getKind()) {
@@ -1492,7 +1492,7 @@ FixupVariantKind(const MCExpr *E) {
case MCExpr::Unary: {
const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
- const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
+ const MCExpr *Sub = fixupVariantKind(UE->getSubExpr());
if (Sub == UE->getSubExpr())
return E;
return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
@@ -1500,8 +1500,8 @@ FixupVariantKind(const MCExpr *E) {
case MCExpr::Binary: {
const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
- const MCExpr *LHS = FixupVariantKind(BE->getLHS());
- const MCExpr *RHS = FixupVariantKind(BE->getRHS());
+ const MCExpr *LHS = fixupVariantKind(BE->getLHS());
+ const MCExpr *RHS = fixupVariantKind(BE->getRHS());
if (LHS == BE->getLHS() && RHS == BE->getRHS())
return E;
return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
@@ -1511,29 +1511,29 @@ FixupVariantKind(const MCExpr *E) {
llvm_unreachable("Invalid expression kind!");
}
-/// ParseExpression. This differs from the default "parseExpression" in that
+/// parseExpression. This differs from the default "parseExpression" in that
/// it handles modifiers.
bool PPCAsmParser::
-ParseExpression(const MCExpr *&EVal) {
+parseExpression(const MCExpr *&EVal) {
// (ELF Platforms)
// Handle \code @l/@ha \endcode
if (getParser().parseExpression(EVal))
return true;
- EVal = FixupVariantKind(EVal);
+ EVal = fixupVariantKind(EVal);
PPCMCExpr::VariantKind Variant;
- const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
+ const MCExpr *E = extractModifierFromExpr(EVal, Variant);
if (E)
EVal = PPCMCExpr::create(Variant, E, getParser().getContext());
return false;
}
-/// ParseOperand
+/// parseOperand
/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
/// rNN for MachO.
-bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
+bool PPCAsmParser::parseOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -1546,7 +1546,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
case AsmToken::Percent: {
MCRegister RegNo;
int64_t IntVal;
- if (MatchRegisterName(RegNo, IntVal))
+ if (matchRegisterName(RegNo, IntVal))
return Error(S, "invalid register name");
Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
@@ -1561,7 +1561,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
case AsmToken::Dollar:
case AsmToken::Exclaim:
case AsmToken::Tilde:
- if (!ParseExpression(EVal))
+ if (!parseExpression(EVal))
break;
// Fall-through
[[fallthrough]];
@@ -1589,7 +1589,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
if (TlsCall && parseOptionalToken(AsmToken::LParen)) {
const MCExpr *TLSSym;
const SMLoc S2 = Parser.getTok().getLoc();
- if (ParseExpression(TLSSym))
+ if (parseExpression(TLSSym))
return Error(S2, "invalid TLS call expression");
E = Parser.getTok().getLoc();
if (parseToken(AsmToken::RParen, "expected ')'"))
@@ -1631,7 +1631,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
switch (getLexer().getKind()) {
case AsmToken::Percent: {
MCRegister RegNo;
- if (MatchRegisterName(RegNo, IntVal))
+ if (matchRegisterName(RegNo, IntVal))
return Error(S, "invalid register name");
break;
}
@@ -1655,7 +1655,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
}
/// Parse an instruction mnemonic followed by its operands.
-bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool PPCAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
// The first operand is the token for the instruction name.
// If the next character is a '+' or '-', we need to add it to the
@@ -1695,11 +1695,11 @@ bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
// Parse the first operand
- if (ParseOperand(Operands))
+ if (parseOperand(Operands))
return true;
while (!parseOptionalToken(AsmToken::EndOfStatement)) {
- if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
+ if (parseToken(AsmToken::Comma) || parseOperand(Operands))
return true;
}
@@ -1731,31 +1731,31 @@ bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
-/// ParseDirective parses the PPC specific directives
-bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
+/// parseDirectives parses the PPC specific directives
+bool PPCAsmParser::parseDirectives(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
- ParseDirectiveWord(2, DirectiveID);
+ parseDirectiveWord(2, DirectiveID);
else if (IDVal == ".llong")
- ParseDirectiveWord(8, DirectiveID);
+ parseDirectiveWord(8, DirectiveID);
else if (IDVal == ".tc")
- ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
+ parseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
else if (IDVal == ".machine")
- ParseDirectiveMachine(DirectiveID.getLoc());
+ parseDirectiveMachine(DirectiveID.getLoc());
else if (IDVal == ".abiversion")
- ParseDirectiveAbiVersion(DirectiveID.getLoc());
+ parseDirectiveAbiVersion(DirectiveID.getLoc());
else if (IDVal == ".localentry")
- ParseDirectiveLocalEntry(DirectiveID.getLoc());
+ parseDirectiveLocalEntry(DirectiveID.getLoc());
else if (IDVal.starts_with(".gnu_attribute"))
- ParseGNUAttribute(DirectiveID.getLoc());
+ parseGNUAttribute(DirectiveID.getLoc());
else
return true;
return false;
}
-/// ParseDirectiveWord
+/// parseDirectiveWord
/// ::= .word [ expression (, expression)* ]
-bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
+bool PPCAsmParser::parseDirectiveWord(unsigned Size, AsmToken ID) {
auto parseOp = [&]() -> bool {
const MCExpr *Value;
SMLoc ExprLoc = getParser().getTok().getLoc();
@@ -1778,9 +1778,9 @@ bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
return false;
}
-/// ParseDirectiveTC
+/// parseDirectiveTC
/// ::= .tc [ symbol (, expression)* ]
-bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
+bool PPCAsmParser::parseDirectiveTC(unsigned Size, AsmToken ID) {
MCAsmParser &Parser = getParser();
// Skip TC symbol, which is only used with XCOFF.
while (getLexer().isNot(AsmToken::EndOfStatement)
@@ -1793,12 +1793,12 @@ bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
getParser().getStreamer().emitValueToAlignment(Align(Size));
// Emit expressions.
- return ParseDirectiveWord(Size, ID);
+ return parseDirectiveWord(Size, ID);
}
-/// ParseDirectiveMachine (ELF platforms)
+/// parseDirectiveMachine (ELF platforms)
/// ::= .machine [ cpu | "push" | "pop" ]
-bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
+bool PPCAsmParser::parseDirectiveMachine(SMLoc L) {
MCAsmParser &Parser = getParser();
if (Parser.getTok().isNot(AsmToken::Identifier) &&
Parser.getTok().isNot(AsmToken::String))
@@ -1823,9 +1823,9 @@ bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
return false;
}
-/// ParseDirectiveAbiVersion
+/// parseDirectiveAbiVersion
/// ::= .abiversion constant-expression
-bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
+bool PPCAsmParser::parseDirectiveAbiVersion(SMLoc L) {
int64_t AbiVersion;
if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
"expected constant expression") ||
@@ -1840,9 +1840,9 @@ bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
return false;
}
-/// ParseDirectiveLocalEntry
+/// parseDirectiveLocalEntry
/// ::= .localentry symbol, expression
-bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
+bool PPCAsmParser::parseDirectiveLocalEntry(SMLoc L) {
StringRef Name;
if (getParser().parseIdentifier(Name))
return Error(L, "expected identifier in '.localentry' directive");
@@ -1863,7 +1863,7 @@ bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
return false;
}
-bool PPCAsmParser::ParseGNUAttribute(SMLoc L) {
+bool PPCAsmParser::parseGNUAttribute(SMLoc L) {
int64_t Tag;
int64_t IntegerValue;
if (!getParser().parseGNUAttribute(L, Tag, IntegerValue))
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6eb2058107610e..9600293d3da71d 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -104,7 +104,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
bool generateImmOutOfRangeError(SMLoc ErrorLoc, int64_t Lower, int64_t Upper,
const Twine &Msg);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -114,7 +114,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
@@ -182,7 +182,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
bool validateInstruction(MCInst &Inst, OperandVector &Operands);
/// Helper for processing MC instructions that have been successfully matched
- /// by MatchAndEmitInstruction. Modifications to the emitted instructions,
+ /// by matchAndEmitInstruction. Modifications to the emitted instructions,
/// like the expansion of pseudo instructions (e.g., "li"), can be performed
/// in this method.
bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
@@ -1376,7 +1376,7 @@ bool RISCVAsmParser::generateImmOutOfRangeError(
return generateImmOutOfRangeError(ErrorLoc, Lower, Upper, Msg);
}
-bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -2732,7 +2732,7 @@ bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
return true;
}
-bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool RISCVAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// Ensure that if the instruction occurs when relaxation is enabled,
@@ -3186,12 +3186,12 @@ bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
ParseInstructionInfo Info;
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
- if (ParseInstruction(Info, FormatName, L, Operands))
+ if (parseInstruction(Info, FormatName, L, Operands))
return true;
unsigned Opcode;
uint64_t ErrorInfo;
- return MatchAndEmitInstruction(L, Opcode, Operands, Parser.getStreamer(),
+ return matchAndEmitInstruction(L, Opcode, Operands, Parser.getStreamer(),
ErrorInfo,
/*MatchingInlineAsm=*/false);
}
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index c1200df5d44dd6..c7a0bebea96943 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -70,14 +70,14 @@ class SparcAsmParser : public MCTargetAsmParser {
/// }
// public interface of the MCTargetAsmParser.
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
@@ -789,7 +789,7 @@ bool SparcAsmParser::expandSETX(MCInst &Inst, SMLoc IDLoc,
return false;
}
-bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool SparcAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
@@ -871,14 +871,14 @@ ParseStatus SparcAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
return ParseStatus::NoMatch;
}
-bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool SparcAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// Validate and reject unavailable mnemonics early before
// running any operand parsing.
// This is needed because some operands (mainly memory ones)
// differ between V8 and V9 ISA and so any operand parsing errors
- // will cause IAS to bail out before it reaches MatchAndEmitInstruction
+ // will cause IAS to bail out before it reaches matchAndEmitInstruction
// (where the instruction as a whole, including the mnemonic, is validated
// once again just before emission).
// As a nice side effect this also allows us to reject unknown
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 7c3898ac67312d..5b26ba08dbdb6b 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -499,9 +499,9 @@ class SystemZAsmParser : public MCTargetAsmParser {
bool RequirePercent, bool RestoreOnFailure);
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -1401,7 +1401,7 @@ ParseStatus SystemZAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
return ParseStatus::Success;
}
-bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
+bool SystemZAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
@@ -1526,7 +1526,7 @@ bool SystemZAsmParser::parseOperand(OperandVector &Operands,
return false;
}
-bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool SystemZAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out,
uint64_t &ErrorInfo,
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index 691fe8fe3aa446..5073894cc7fbe1 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -51,7 +51,7 @@ class VEAsmParser : public MCTargetAsmParser {
/// }
// public interface of the MCTargetAsmParser.
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -59,7 +59,7 @@ class VEAsmParser : public MCTargetAsmParser {
int parseRegisterName(MCRegister (*matchFn)(StringRef));
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
@@ -760,7 +760,7 @@ class VEOperand : public MCParsedAsmOperand {
} // end anonymous namespace
-bool VEAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool VEAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -965,7 +965,7 @@ static void applyMnemonicAliases(StringRef &Mnemonic,
const FeatureBitset &Features,
unsigned VariantID);
-bool VEAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool VEAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
// If the target architecture uses MnemonicAlias, call it here to parse
// operands correctly.
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index 4fef5fa0ef2208..8e8d08f775638b 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -562,7 +562,7 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser {
}
}
- bool ParseInstruction(ParseInstructionInfo & /*Info*/, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo & /*Info*/, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override {
// Note: Name does NOT point into the sourcecode, but to a local, so
// use NameLoc instead.
@@ -1127,7 +1127,7 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser {
}
}
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned & /*Opcode*/,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned & /*Opcode*/,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override {
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 735f9dcefb97f7..96bf633145cb4e 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1195,7 +1195,7 @@ class X86AsmParser : public MCTargetAsmParser {
/// instrumentation around Inst.
void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
@@ -1215,7 +1215,7 @@ class X86AsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm);
- bool OmitRegisterFromClobberLists(unsigned RegNo) override;
+ bool omitRegisterFromClobberLists(unsigned RegNo) override;
/// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
/// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
@@ -1290,10 +1290,10 @@ class X86AsmParser : public MCTargetAsmParser {
bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+ bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool ParseDirective(AsmToken DirectiveID) override;
+ bool parseDirectives(AsmToken DirectiveID) override;
};
} // end anonymous namespace
@@ -3186,7 +3186,7 @@ bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
return Parser.parsePrimaryExpr(Res, EndLoc, nullptr);
}
-bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+bool X86AsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
MCAsmParser &Parser = getParser();
InstInfo = &Info;
@@ -4121,7 +4121,7 @@ static unsigned getPrefixes(OperandVector &Operands) {
return Result;
}
-bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+bool X86AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
bool MatchingInlineAsm) {
@@ -4659,11 +4659,11 @@ bool X86AsmParser::matchAndEmitIntelInstruction(
MatchingInlineAsm);
}
-bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
+bool X86AsmParser::omitRegisterFromClobberLists(unsigned RegNo) {
return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
}
-bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
+bool X86AsmParser::parseDirectives(AsmToken DirectiveID) {
MCAsmParser &Parser = getParser();
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal.starts_with(".arch"))
>From 8897298e8f9da7f4f26ba22486d27bc2f11b2480 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 13 Sep 2024 21:02:21 +0000
Subject: [PATCH 2/4] apply clang format
---
.../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 ++--
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 12 +++++-------
3 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 72c51f5ab09a61..9e24a9eebeb40e 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -235,8 +235,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
-/// @name Auto-generated Match Functions
-/// {
+ /// @name Auto-generated Match Functions
+ /// {
#define GET_ASSEMBLER_HEADER
#include "AArch64GenAsmMatcher.inc"
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 51de0f8ffb12d9..2854f48fce34dd 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6394,8 +6394,8 @@ static void applyMnemonicAliases(StringRef &Mnemonic,
unsigned VariantID);
bool AMDGPUAsmParser::parseInstruction(ParseInstructionInfo &Info,
- StringRef Name,
- SMLoc NameLoc, OperandVector &Operands) {
+ StringRef Name, SMLoc NameLoc,
+ OperandVector &Operands) {
// Add the instruction mnemonic
Name = parseMnemonicSuffix(Name);
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 8a369154d5371f..7051a7abd90f13 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1375,9 +1375,9 @@ ParseStatus PPCAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
/// variant, return the corresponding PPCMCExpr::VariantKind,
/// and a modified expression using the default symbol variant.
/// Otherwise, return NULL.
-const MCExpr *PPCAsmParser::
-extractModifierFromExpr(const MCExpr *E,
- PPCMCExpr::VariantKind &Variant) {
+const MCExpr *
+PPCAsmParser::extractModifierFromExpr(const MCExpr *E,
+ PPCMCExpr::VariantKind &Variant) {
MCContext &Context = getParser().getContext();
Variant = PPCMCExpr::VK_PPC_None;
@@ -1464,8 +1464,7 @@ extractModifierFromExpr(const MCExpr *E,
/// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
/// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
/// FIXME: This is a hack.
-const MCExpr *PPCAsmParser::
-fixupVariantKind(const MCExpr *E) {
+const MCExpr *PPCAsmParser::fixupVariantKind(const MCExpr *E) {
MCContext &Context = getParser().getContext();
switch (E->getKind()) {
@@ -1513,8 +1512,7 @@ fixupVariantKind(const MCExpr *E) {
/// parseExpression. This differs from the default "parseExpression" in that
/// it handles modifiers.
-bool PPCAsmParser::
-parseExpression(const MCExpr *&EVal) {
+bool PPCAsmParser::parseExpression(const MCExpr *&EVal) {
// (ELF Platforms)
// Handle \code @l/@ha \endcode
if (getParser().parseExpression(EVal))
>From 2d838e42e90f947640cbf5264a524c219c569161 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 17 Sep 2024 20:22:18 +0000
Subject: [PATCH 3/4] Address review comments
1. remove function name from doc above functions being updated.
2. leave ParseDirective() as is as it's deprecated.
---
llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 8 ++++----
llvm/lib/MC/MCParser/MCTargetAsmParser.cpp | 6 +++---
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 9 ++++-----
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 ++--
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 +++---
llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp | 3 +--
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 6 +++---
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 4 ++--
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 6 +++---
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 4 ++--
10 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
index 93e27a02aeffcb..54ae436d90b283 100644
--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
@@ -426,7 +426,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
virtual ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) = 0;
- /// ParseInstruction - Parse one assembly instruction.
+ /// Parse one assembly instruction.
///
/// The parser is positioned following the instruction name. The target
/// specific instruction parser should parse the entire instruction and
@@ -446,7 +446,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
return parseInstruction(Info, Name, Token.getLoc(), Operands);
}
- /// parseDirectives - Parse a target specific assembler directive
+ /// ParseDirective - Parse a target specific assembler directive
/// This method is deprecated, use 'parseDirective' instead.
///
/// The parser is positioned following the directive name. The target
@@ -457,7 +457,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// end-of-statement token and false is returned.
///
/// \param DirectiveID - the identifier token of the directive.
- virtual bool parseDirectives(AsmToken DirectiveID) { return true; }
+ virtual bool ParseDirective(AsmToken DirectiveID) { return true; }
/// Parses a target-specific assembler directive.
///
@@ -471,7 +471,7 @@ class MCTargetAsmParser : public MCAsmParserExtension {
/// \param DirectiveID - The token identifying the directive.
virtual ParseStatus parseDirective(AsmToken DirectiveID);
- /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
+ /// Recognize a series of operands of a parsed
/// instruction as an actual MCInst and emit it to the specified MCStreamer.
/// This returns false on success and returns true on failure to match.
///
diff --git a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
index 931d5888c9034c..665d92eb9a21c5 100644
--- a/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
+++ b/llvm/lib/MC/MCParser/MCTargetAsmParser.cpp
@@ -31,15 +31,15 @@ const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
ParseStatus MCTargetAsmParser::parseDirective(AsmToken DirectiveID) {
SMLoc StartTokLoc = getTok().getLoc();
- // Delegate to parseDirectives by default for transition period. Once the
+ // Delegate to ParseDirective by default for transition period. Once the
// transition is over, this method should just return NoMatch.
- bool Res = parseDirectives(DirectiveID);
+ bool Res = ParseDirective(DirectiveID);
// Some targets erroneously report success after emitting an error.
if (getParser().hasPendingError())
return ParseStatus::Failure;
- // parseDirectives returns true if there was an error or if the directive is
+ // ParseDirective returns true if there was an error or if the directive is
// not target-specific. Disambiguate the two cases by comparing position of
// the lexer before and after calling the method: if no tokens were consumed,
// there was no match, otherwise there was a failure.
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 9e24a9eebeb40e..e42e7eb57d8dd8 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -326,7 +326,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -5086,8 +5086,7 @@ bool AArch64AsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
return false;
}
-/// parseInstruction - Parse an AArch64 instruction mnemonic followed by its
-/// operands.
+/// Parse an AArch64 instruction mnemonic followed by its operands.
bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
@@ -6798,8 +6797,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// parseDirectives parses the arm specific directives
-bool AArch64AsmParser::parseDirectives(AsmToken DirectiveID) {
+/// ParseDirectives parses the arm specific directives
+bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
bool IsCOFF = Format == MCContext::IsCOFF;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 2854f48fce34dd..bab3f8a08781da 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1601,7 +1601,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
OperandMode Mode = OperandMode_Default);
StringRef parseMnemonicSuffix(StringRef Name);
@@ -6194,7 +6194,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
return false;
}
-bool AMDGPUAsmParser::parseDirectives(AsmToken DirectiveID) {
+bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getString();
if (isHsaAbi(getSTI())) {
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 64e4dae5365085..7d74f86c164fc7 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -714,7 +714,7 @@ class ARMAsmParser : public MCTargetAsmParser {
SMLoc &EndLoc) override;
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -11427,8 +11427,8 @@ bool ARMAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// parseDirectives parses the arm specific directives
-bool ARMAsmParser::parseDirectives(AsmToken DirectiveID) {
+/// ParseDirective parses the arm specific directives
+bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
bool IsCOFF = Format == MCContext::IsCOFF;
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
index 98ab0f2bd399b5..06b7743e0cd310 100644
--- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
+++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
@@ -483,8 +483,7 @@ ParseStatus BPFAsmParser::parseImmediate(OperandVector &Operands) {
return ParseStatus::Success;
}
-/// parseInstruction - Parse an BPF instruction which is in BPF verifier
-/// format.
+/// Parse an BPF instruction which is in BPF verifier format.
bool BPFAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) {
// The first operand could be either register or actually an operator.
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index 74616fa7da1ead..62f188957cccf5 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -188,7 +188,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
OperandVector &Operands) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
};
/// HexagonOperand - Instances of this class represent a parsed Hexagon machine
@@ -710,8 +710,8 @@ bool HexagonAsmParser::parseDirectiveAttribute(SMLoc L) {
return false;
}
-/// parseDirectives parses the Hexagon specific directives
-bool HexagonAsmParser::parseDirectives(AsmToken DirectiveID) {
+/// ParseDirective parses the Hexagon specific directives
+bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal.lower() == ".falign")
return ParseDirectiveFalign(256, DirectiveID.getLoc());
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 91390ce028d17e..7888c57363ed33 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -193,7 +193,7 @@ class MipsAsmParser : public MCTargetAsmParser {
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
ParseStatus parseMemOperand(OperandVector &Operands);
ParseStatus matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
@@ -8630,7 +8630,7 @@ bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
return false;
}
-bool MipsAsmParser::parseDirectives(AsmToken DirectiveID) {
+bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
// This returns false if this function recognizes the directive
// regardless of whether it is successfully handles or reports an
// error. Otherwise it returns true to give the generic parser a
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 7051a7abd90f13..ccd703cee84d24 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -153,7 +153,7 @@ class PPCAsmParser : public MCTargetAsmParser {
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
@@ -1729,8 +1729,8 @@ bool PPCAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
-/// parseDirectives parses the PPC specific directives
-bool PPCAsmParser::parseDirectives(AsmToken DirectiveID) {
+/// ParseDirective parses the PPC specific directives
+bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
parseDirectiveWord(2, DirectiveID);
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 96bf633145cb4e..97079cba143ab3 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1293,7 +1293,7 @@ class X86AsmParser : public MCTargetAsmParser {
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
- bool parseDirectives(AsmToken DirectiveID) override;
+ bool ParseDirective(AsmToken DirectiveID) override;
};
} // end anonymous namespace
@@ -4663,7 +4663,7 @@ bool X86AsmParser::omitRegisterFromClobberLists(unsigned RegNo) {
return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
}
-bool X86AsmParser::parseDirectives(AsmToken DirectiveID) {
+bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
MCAsmParser &Parser = getParser();
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal.starts_with(".arch"))
>From 1d6b8c834c0d4370057ff61bba9d9963fa5cb617 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 17 Sep 2024 20:34:46 +0000
Subject: [PATCH 4/4] clean up doc that contain function names
---
.../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 2 +-
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 13 ++++---------
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index e42e7eb57d8dd8..4f6131fd835577 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6797,7 +6797,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Implement any new match types added!");
}
-/// ParseDirectives parses the arm specific directives
+/// ParseDirective parses the arm specific directives
bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
const MCContext::Environment Format = getContext().getObjectFileType();
bool IsMachO = Format == MCContext::IsMachO;
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index ccd703cee84d24..597a976b076a52 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1510,8 +1510,8 @@ const MCExpr *PPCAsmParser::fixupVariantKind(const MCExpr *E) {
llvm_unreachable("Invalid expression kind!");
}
-/// parseExpression. This differs from the default "parseExpression" in that
-/// it handles modifiers.
+/// This differs from the default "parseExpression" in that it handles
+/// modifiers.
bool PPCAsmParser::parseExpression(const MCExpr *&EVal) {
// (ELF Platforms)
// Handle \code @l/@ha \endcode
@@ -1528,7 +1528,6 @@ bool PPCAsmParser::parseExpression(const MCExpr *&EVal) {
return false;
}
-/// parseOperand
/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
/// rNN for MachO.
bool PPCAsmParser::parseOperand(OperandVector &Operands) {
@@ -1729,7 +1728,7 @@ bool PPCAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
-/// ParseDirective parses the PPC specific directives
+/// Parses the PPC specific directives
bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
@@ -1751,7 +1750,6 @@ bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
return false;
}
-/// parseDirectiveWord
/// ::= .word [ expression (, expression)* ]
bool PPCAsmParser::parseDirectiveWord(unsigned Size, AsmToken ID) {
auto parseOp = [&]() -> bool {
@@ -1776,7 +1774,6 @@ bool PPCAsmParser::parseDirectiveWord(unsigned Size, AsmToken ID) {
return false;
}
-/// parseDirectiveTC
/// ::= .tc [ symbol (, expression)* ]
bool PPCAsmParser::parseDirectiveTC(unsigned Size, AsmToken ID) {
MCAsmParser &Parser = getParser();
@@ -1794,7 +1791,7 @@ bool PPCAsmParser::parseDirectiveTC(unsigned Size, AsmToken ID) {
return parseDirectiveWord(Size, ID);
}
-/// parseDirectiveMachine (ELF platforms)
+/// ELF platforms.
/// ::= .machine [ cpu | "push" | "pop" ]
bool PPCAsmParser::parseDirectiveMachine(SMLoc L) {
MCAsmParser &Parser = getParser();
@@ -1821,7 +1818,6 @@ bool PPCAsmParser::parseDirectiveMachine(SMLoc L) {
return false;
}
-/// parseDirectiveAbiVersion
/// ::= .abiversion constant-expression
bool PPCAsmParser::parseDirectiveAbiVersion(SMLoc L) {
int64_t AbiVersion;
@@ -1838,7 +1834,6 @@ bool PPCAsmParser::parseDirectiveAbiVersion(SMLoc L) {
return false;
}
-/// parseDirectiveLocalEntry
/// ::= .localentry symbol, expression
bool PPCAsmParser::parseDirectiveLocalEntry(SMLoc L) {
StringRef Name;
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