[llvm] [llvm][ARM][CodeGen] Disable MEMCPY LDM/STM inlining for Cortex v7-m (PR #106378)
Nashe Mncube via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 18 07:51:51 PDT 2024
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@@ -465,6 +465,16 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
/// True if fast-isel is used.
bool useFastISel() const;
+ /// True if ARMISD::MEMCPY should not be created/expanded specially (e.g.
+ /// as LDM/STM pairs).
+ bool wantsMEMCPYAsLdSt() const { return HasV7Ops && ARMProcClass == MClass; }
+
+ /// True if volatile ARMISD::MEMCPY should not be created/expanded specially
+ /// (e.g. as LDM/STM pairs).
+ bool wantsVolatileMEMCPYAsLdSt() const {
+ return ARMProcClass == MClass && HasV6Ops && !HasV7Ops;
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nasherm wrote:
Done
https://github.com/llvm/llvm-project/pull/106378
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