[llvm] [AMDGPU] Add hazard workarounds to insertIndirectBranch (PR #109127)

[Matt Arsenault via llvm-commits]

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@@ -2867,6 +2867,12 @@ void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
 
+  // Note: as this is used after hazard recognizer we need to apply some hazard
+  // workarounds directly.
+  const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
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arsenm wrote:

ST is already a member of SIInstrInfo 

https://github.com/llvm/llvm-project/pull/109127