[llvm] e0a1637 - [AMDGPU] Omit isReg() check for all_uses() in SIInsertWaitcnts. NFC. (#109041)

via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 18 00:08:27 PDT 2024


Author: Stanislav Mekhanoshin
Date: 2024-09-18T00:08:23-07:00
New Revision: e0a16371c6cce47e2b0626225a727b458ebe7666

URL: https://github.com/llvm/llvm-project/commit/e0a16371c6cce47e2b0626225a727b458ebe7666
DIFF: https://github.com/llvm/llvm-project/commit/e0a16371c6cce47e2b0626225a727b458ebe7666.diff

LOG: [AMDGPU] Omit isReg() check for all_uses() in SIInsertWaitcnts. NFC. (#109041)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index fd9fe1196b7853..a5668272601384 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -820,7 +820,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
                  Inst.getOpcode() != AMDGPU::DS_CONSUME &&
                  Inst.getOpcode() != AMDGPU::DS_ORDERED_COUNT) {
         for (const MachineOperand &Op : Inst.all_uses()) {
-          if (Op.isReg() && TRI->isVectorRegister(*MRI, Op.getReg()))
+          if (TRI->isVectorRegister(*MRI, Op.getReg()))
             setExpScore(&Inst, TRI, MRI, Op, CurrScore);
         }
       }
@@ -872,7 +872,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
         }
       }
       for (const MachineOperand &Op : Inst.all_uses()) {
-        if (Op.isReg() && TRI->isVectorRegister(*MRI, Op.getReg()))
+        if (TRI->isVectorRegister(*MRI, Op.getReg()))
           setExpScore(&Inst, TRI, MRI, Op, CurrScore);
       }
     }
@@ -2327,7 +2327,7 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML,
           HasVMemStore = true;
       }
       for (const MachineOperand &Op : MI.all_uses()) {
-        if (!Op.isReg() || !TRI->isVectorRegister(*MRI, Op.getReg()))
+        if (!TRI->isVectorRegister(*MRI, Op.getReg()))
           continue;
         RegInterval Interval = Brackets.getRegInterval(&MI, MRI, TRI, Op);
         // Vgpr use


        


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