[llvm] [AMDGPU] Handle subregisters properly in generic operand legalizer (PR #108496)

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github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff b43302372f592fd48a22d32b2603f8efee40a88e df08032694e8b1d335e3f2cb7f3688e39d7257fc --extensions cpp -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 380f63c626..6c54b5d3d1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6231,10 +6231,11 @@ void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
     return;
 
   Register DstReg = MRI.createVirtualRegister(DstRC);
-  auto Copy = BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).addReg(OpReg);
+  auto Copy =
+      BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).addReg(OpReg);
 
   Op.setReg(DstReg);
-  
+
   MachineInstr *Def = MRI.getVRegDef(OpReg);
   if (!Def)
     return;

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https://github.com/llvm/llvm-project/pull/108496