[llvm] [NVPTX] Emit ld.v4.b16 for loading <4 x bfloat> (PR #109069)

[Ahmed S. Taei via llvm-commits]

https://github.com/asaadaldien updated https://github.com/llvm/llvm-project/pull/109069

>From 61dae49fe7a6b10a65c7ca7b28bc6526490c41d4 Mon Sep 17 00:00:00 2001
From: "Ahmed S. Taei" <ataei at modular.com>
Date: Tue, 17 Sep 2024 16:54:04 -0700
Subject: [PATCH] [NVPTX] Emit ld.v4.b16 for loading <4 x bfloat>

This PR enables emitting a single load instruction for <4 x bfloat>, otherwise, 2 ld.b32 loads are generated.
---
 llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 1 +
 llvm/test/CodeGen/NVPTX/vector-loads.ll     | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index c5a40e4308860c..31a5e937adae96 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -6179,6 +6179,7 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
   case MVT::v4i16:
   case MVT::v4i32:
   case MVT::v4f16:
+  case MVT::v4bf16:
   case MVT::v4f32:
   case MVT::v8f16:  // <4 x f16x2>
   case MVT::v8bf16: // <4 x bf16x2>
diff --git a/llvm/test/CodeGen/NVPTX/vector-loads.ll b/llvm/test/CodeGen/NVPTX/vector-loads.ll
index 9322b9e0fe6c82..f582ebc166dd0d 100644
--- a/llvm/test/CodeGen/NVPTX/vector-loads.ll
+++ b/llvm/test/CodeGen/NVPTX/vector-loads.ll
@@ -198,3 +198,12 @@ define void @extv8f16_generic_a4(ptr noalias readonly align 16 %dst, ptr noalias
 
 
 !1 = !{i32 0, i32 64}
+
+; CHECK-LABEL: bf16_v4_align_load_store
+define dso_local void @bf16_v4_align_load_store(ptr noundef %0, ptr noundef %1) #0 {
+  ; CHECK: ld.v4.b16
+  ; CHECK: st.v4.b16
+  %3 = load <4 x bfloat>, ptr %1, align 8
+  store <4 x bfloat> %3, ptr %0, align 8
+  ret void
+}