[llvm] [RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (PR #108991)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

@tobias-stadler Thank you for the insights. I took the advice and began to port #108859 to the instruction selector. I quickly ran into the problem that G_* instructions created in the instruction selector are not regbankselected. If you check out #108859, you can see that `lowerInsertSubvector` and its children have many calls to `MIB.buildXXX` (around 10 static calls to `MIB.buildXXX`). It seems quite yucky to have to manually regbankselect/constrain all all over the lowering/selection code. I am wondering if you have run into this problem and what your thoughts are on it.

https://github.com/llvm/llvm-project/pull/108991