[llvm] [RISCV] Remove unnecessary vand.vi from vXi1 and nvXvi1 VECTOR_REVERSE codegen. (PR #109071)

[Philip Reames via llvm-commits]

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@@ -10804,7 +10804,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
     MVT WidenVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount());
     SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, Op.getOperand(0));
     SDValue Op2 = DAG.getNode(ISD::VECTOR_REVERSE, DL, WidenVT, Op1);
-    return DAG.getNode(ISD::TRUNCATE, DL, VecVT, Op2);
+    return DAG.getSetCC(DL, VecVT, Op2,
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preames wrote:

Optional follow up - maybe we should add a computeKnownBits call to lowerVectorMaskTruncLike to bypass the AND_VL?  Or alternatively, add known bits support for AND_VL?

https://github.com/llvm/llvm-project/pull/109071