[llvm] update P7 v4i8 load cost (PR #108261)

[via llvm-commits]

https://github.com/RolandF77 updated https://github.com/llvm/llvm-project/pull/108261

>From 36775312d6ea68036ce63a55490a32fa6877bdf0 Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Wed, 11 Sep 2024 18:08:25 +0000
Subject: [PATCH 1/2] update P7 v4i8 load cost

---
 llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 14 ++++++++++----
 .../Analysis/CostModel/PowerPC/vsr_load_32_64.ll   |  7 +++++--
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index b7bdbeb535d526..df0047022a2c04 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -802,12 +802,18 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
   // explicitly check this case. There are also corresponding store
   // instructions.
   unsigned MemBytes = Src->getPrimitiveSizeInBits();
-  if (ST->hasVSX() && IsAltivecType &&
-      (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
-    return 1;
+  Align AlignBytes = Alignment ? *Alignment : Align(1);
+  unsigned SrcBytes = LT.second.getStoreSize();
+  if (ST->hasVSX() && IsAltivecType) {
+    if (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))
+      return 1;
+    // Use lfiwax/xxspltw
+    if (Opcode == Instruction::Load && MemBytes == 32)
+      if (AlignBytes < SrcBytes || Cost > 2)
+        return 2;
+  }
 
   // Aligned loads and stores are easy.
-  unsigned SrcBytes = LT.second.getStoreSize();
   if (!SrcBytes || !Alignment || *Alignment >= SrcBytes)
     return Cost;
 
diff --git a/llvm/test/Analysis/CostModel/PowerPC/vsr_load_32_64.ll b/llvm/test/Analysis/CostModel/PowerPC/vsr_load_32_64.ll
index 54cafa0ae59f39..0e7e89c18c1cba 100644
--- a/llvm/test/Analysis/CostModel/PowerPC/vsr_load_32_64.ll
+++ b/llvm/test/Analysis/CostModel/PowerPC/vsr_load_32_64.ll
@@ -1,18 +1,21 @@
 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck --check-prefix=P7 %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @loads(i32 %arg) {
   ; CHECK: cost of 1 {{.*}} load
+  ; P7: cost of 2 {{.*}} load
   load <4 x i8>, ptr undef, align 1
 
-  ; CHECK: cost of 1 {{.*}} load
+  ; CHECK, P7: cost of 1 {{.*}} load
   load <8 x i8>, ptr undef, align 1
 
   ; CHECK: cost of 1 {{.*}} load
+  ; P7: cost of 2 {{.*}} load
   load <2 x i16>, ptr undef, align 2
 
-  ; CHECK: cost of 1 {{.*}} load
+  ; CHECK, P7: cost of 1 {{.*}} load
   load <4 x i16>, ptr undef, align 2
 
   ret i32 undef

>From 7103010cdb30a5b69f9e187c87e05ede5e8b3382 Mon Sep 17 00:00:00 2001
From: Roland Froese <froese at ca.ibm.com>
Date: Tue, 17 Sep 2024 21:06:05 +0000
Subject: [PATCH 2/2] address comments

---
 llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index df0047022a2c04..de954dccadf59d 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -808,9 +808,8 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
     if (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))
       return 1;
     // Use lfiwax/xxspltw
-    if (Opcode == Instruction::Load && MemBytes == 32)
-      if (AlignBytes < SrcBytes || Cost > 2)
-        return 2;
+    if (Opcode == Instruction::Load && MemBytes == 32 && AlignBytes < SrcBytes)
+      return 2;
   }
 
   // Aligned loads and stores are easy.