[llvm] [LLVM][TableGen] Change DAGISel code to use const RecordKeeper (PR #109038)
Rahul Joshi via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 17 13:07:59 PDT 2024
https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/109038
Change DAGISel code to use const RecordKeeper.
>From 5d697f926e90204e796c9ee6a54ff2361f52133e Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Tue, 17 Sep 2024 13:06:51 -0700
Subject: [PATCH] [LLVM][TableGen] Change DAGISel code to use const
RecordKeeper
---
llvm/utils/TableGen/DAGISelEmitter.cpp | 21 +++++++++++----------
llvm/utils/TableGen/DAGISelMatcherGen.cpp | 20 ++++++++++----------
2 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 6c72103f6251f5..c41afbf2dec40a 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -25,11 +25,11 @@ namespace {
/// DAGISelEmitter - The top-level class which coordinates construction
/// and emission of the instruction selector.
class DAGISelEmitter {
- RecordKeeper &Records; // Just so we can get at the timing functions.
- CodeGenDAGPatterns CGP;
+ const RecordKeeper &Records; // Just so we can get at the timing functions.
+ const CodeGenDAGPatterns CGP;
public:
- explicit DAGISelEmitter(RecordKeeper &R) : Records(R), CGP(R) {}
+ explicit DAGISelEmitter(const RecordKeeper &R) : Records(R), CGP(R) {}
void run(raw_ostream &OS);
};
} // End anonymous namespace
@@ -81,8 +81,8 @@ namespace {
// In particular, we want to match maximal patterns first and lowest cost within
// a particular complexity first.
struct PatternSortingPredicate {
- PatternSortingPredicate(CodeGenDAGPatterns &cgp) : CGP(cgp) {}
- CodeGenDAGPatterns &CGP;
+ PatternSortingPredicate(const CodeGenDAGPatterns &cgp) : CGP(cgp) {}
+ const CodeGenDAGPatterns &CGP;
bool operator()(const PatternToMatch *LHS, const PatternToMatch *RHS) {
const TreePatternNode < = LHS->getSrcPattern();
@@ -132,7 +132,8 @@ struct PatternSortingPredicate {
} // End anonymous namespace
void DAGISelEmitter::run(raw_ostream &OS) {
- Records.startTimer("Parse patterns");
+ RecordKeeper &MutableRC = const_cast<RecordKeeper &>(Records);
+ MutableRC.startTimer("Parse patterns");
emitSourceFileHeader("DAG Instruction Selector for the " +
CGP.getTargetInfo().getName().str() + " target",
OS);
@@ -163,7 +164,7 @@ void DAGISelEmitter::run(raw_ostream &OS) {
});
// Add all the patterns to a temporary list so we can sort them.
- Records.startTimer("Sort patterns");
+ MutableRC.startTimer("Sort patterns");
std::vector<const PatternToMatch *> Patterns;
for (const PatternToMatch &PTM : CGP.ptms())
Patterns.push_back(&PTM);
@@ -173,7 +174,7 @@ void DAGISelEmitter::run(raw_ostream &OS) {
llvm::stable_sort(Patterns, PatternSortingPredicate(CGP));
// Convert each variant of each pattern into a Matcher.
- Records.startTimer("Convert to matchers");
+ MutableRC.startTimer("Convert to matchers");
SmallVector<Matcher *, 0> PatternMatchers;
for (const PatternToMatch *PTM : Patterns) {
for (unsigned Variant = 0;; ++Variant) {
@@ -187,12 +188,12 @@ void DAGISelEmitter::run(raw_ostream &OS) {
std::unique_ptr<Matcher> TheMatcher =
std::make_unique<ScopeMatcher>(std::move(PatternMatchers));
- Records.startTimer("Optimize matchers");
+ MutableRC.startTimer("Optimize matchers");
OptimizeMatcher(TheMatcher, CGP);
// Matcher->dump();
- Records.startTimer("Emit matcher table");
+ MutableRC.startTimer("Emit matcher table");
EmitMatcherTable(TheMatcher.get(), CGP, OS);
}
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index 5cb393ae7a538d..e159cf1bbefd33 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -23,7 +23,7 @@ using namespace llvm;
/// getRegisterValueType - Look up and return the ValueType of the specified
/// register. If the register is a member of multiple register classes, they
/// must all have the same type.
-static MVT::SimpleValueType getRegisterValueType(Record *R,
+static MVT::SimpleValueType getRegisterValueType(const Record *R,
const CodeGenTarget &T) {
bool FoundRC = false;
MVT::SimpleValueType VT = MVT::Other;
@@ -91,7 +91,7 @@ class MatcherGen {
/// PhysRegInputs - List list has an entry for each explicitly specified
/// physreg input to the pattern. The first elt is the Register node, the
/// second is the recorded slot number the input pattern match saved it in.
- SmallVector<std::pair<Record *, unsigned>, 2> PhysRegInputs;
+ SmallVector<std::pair<const Record *, unsigned>, 2> PhysRegInputs;
/// Matcher - This is the top level of the generated matcher, the result.
Matcher *TheMatcher;
@@ -220,13 +220,13 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode &N) {
return;
}
- DefInit *DI = dyn_cast<DefInit>(N.getLeafValue());
+ const DefInit *DI = dyn_cast<DefInit>(N.getLeafValue());
if (!DI) {
errs() << "Unknown leaf kind: " << N << "\n";
abort();
}
- Record *LeafRec = DI->getDef();
+ const Record *LeafRec = DI->getDef();
// A ValueType leaf node can represent a register when named, or itself when
// unnamed.
@@ -673,7 +673,7 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
// If this is an explicit register reference, handle it.
if (DefInit *DI = dyn_cast<DefInit>(N.getLeafValue())) {
- Record *Def = DI->getDef();
+ const Record *Def = DI->getDef();
if (Def->isSubClassOf("Register")) {
const CodeGenRegister *Reg = CGP.getTargetInfo().getRegBank().getReg(Def);
AddMatcher(new EmitRegisterMatcher(Reg, N.getSimpleType(0)));
@@ -690,7 +690,7 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode &N,
if (Def->getName() == "undef_tied_input") {
MVT::SimpleValueType ResultVT = N.getSimpleType(0);
auto IDOperandNo = NextRecordedOperandNo++;
- Record *ImpDef = Def->getRecords().getDef("IMPLICIT_DEF");
+ const Record *ImpDef = Def->getRecords().getDef("IMPLICIT_DEF");
CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(ImpDef);
AddMatcher(new EmitNodeMatcher(II, ResultVT, std::nullopt, false, false,
false, false, -1, IDOperandNo));
@@ -907,11 +907,11 @@ void MatcherGen::EmitResultInstructionAsOperand(
if (isRoot && !Pattern.getDstRegs().empty()) {
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
- Record *HandledReg = nullptr;
+ const Record *HandledReg = nullptr;
if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
HandledReg = II.ImplicitDefs[0];
- for (Record *Reg : Pattern.getDstRegs()) {
+ for (const Record *Reg : Pattern.getDstRegs()) {
if (!Reg->isSubClassOf("Register") || Reg == HandledReg)
continue;
ResultVTs.push_back(getRegisterValueType(Reg, CGT));
@@ -1042,7 +1042,7 @@ void MatcherGen::EmitResultCode() {
if (!Pattern.getDstRegs().empty()) {
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
- Record *HandledReg = nullptr;
+ const Record *HandledReg = nullptr;
const TreePatternNode &DstPat = Pattern.getDstPattern();
if (!DstPat.isLeaf() && DstPat.getOperator()->isSubClassOf("Instruction")) {
const CodeGenTarget &CGT = CGP.getTargetInfo();
@@ -1052,7 +1052,7 @@ void MatcherGen::EmitResultCode() {
HandledReg = II.ImplicitDefs[0];
}
- for (Record *Reg : Pattern.getDstRegs()) {
+ for (const Record *Reg : Pattern.getDstRegs()) {
if (!Reg->isSubClassOf("Register") || Reg == HandledReg)
continue;
++NumSrcResults;
More information about the llvm-commits
mailing list