[llvm] 594579b - [RISCV] Autogenerate compress-opt-select.ll
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 17 08:47:29 PDT 2024
Author: Philip Reames
Date: 2024-09-17T08:47:20-07:00
New Revision: 594579b7af82dab786bb75786451ca582543a697
URL: https://github.com/llvm/llvm-project/commit/594579b7af82dab786bb75786451ca582543a697
DIFF: https://github.com/llvm/llvm-project/commit/594579b7af82dab786bb75786451ca582543a697.diff
LOG: [RISCV] Autogenerate compress-opt-select.ll
I realized after spending way too much time looking at this, that
we can avoid objdump entirely here by having the assembly simply
not print the aliases. Once we do that, we can simply autogen
this test, and updates become trivial and understandable.
Added:
Modified:
llvm/test/CodeGen/RISCV/compress-opt-select.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/compress-opt-select.ll b/llvm/test/CodeGen/RISCV/compress-opt-select.ll
index 2336d9f90dc116..2667fde89e9354 100644
--- a/llvm/test/CodeGen/RISCV/compress-opt-select.ll
+++ b/llvm/test/CodeGen/RISCV/compress-opt-select.ll
@@ -1,69 +1,118 @@
-; This test is designed to run 4 times, once with function attribute +c,
-; once with function attribute -c for eq/ne in icmp
-; The optimization should appear only with +c, otherwise default isel should be
-; choosen.
-;
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
-; RUN: -disable-block-placement < %s \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d \
+; RUN: -riscv-no-aliases < %s \
; RUN: | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
-; RUN: -disable-block-placement < %s \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d \
+; RUN: -riscv-no-aliases < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <ne_small_pos>:
-; RV32IFDC: c.li [[REG:.*]], 0x14
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_small_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x14
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_small_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_small_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, 20
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: bne a1, a2, .LBB0_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB0_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_small_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 20
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB0_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB0_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, 20
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <ne_small_neg>:
-; RV32IFDC: c.li [[REG:.*]], -0x14
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_small_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x14
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_small_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_small_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, -20
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: bne a1, a2, .LBB1_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB1_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_small_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -20
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB1_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB1_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, -20
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <ne_small_edge_pos>:
-; RV32IFDC: c.li [[REG:.*]], 0x1f
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_small_edge_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x1f
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_small_edge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_small_edge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, 31
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: bne a1, a2, .LBB2_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB2_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_small_edge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 31
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB2_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB2_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, 31
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <ne_small_edge_neg>:
-; RV32IFDC: c.li [[REG:.*]], -0x20
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_small_edge_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x20
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_small_edge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_small_edge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, -32
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: bne a1, a2, .LBB3_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB3_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_small_edge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -32
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB3_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB3_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, -32
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -71,14 +120,27 @@ define i32 @ne_small_edge_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <ne_medium_ledge_pos>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x21
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_medium_ledge_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x21
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_medium_ledge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_medium_ledge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, -33
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.bnez a1, .LBB4_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB4_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_medium_ledge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 33
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB4_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB4_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, 33
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -86,14 +148,27 @@ define i32 @ne_medium_ledge_pos(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <ne_medium_ledge_neg>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_medium_ledge_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x21
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_medium_ledge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_medium_ledge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, 33
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.bnez a1, .LBB5_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB5_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_medium_ledge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -33
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB5_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB5_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, -33
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -101,14 +176,27 @@ define i32 @ne_medium_ledge_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <ne_medium_pos>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_medium_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x3f
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_medium_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_medium_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, -63
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.bnez a1, .LBB6_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB6_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_medium_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 63
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB6_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB6_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, 63
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -116,14 +204,27 @@ define i32 @ne_medium_pos(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <ne_medium_neg>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_medium_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x3f
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_medium_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_medium_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, 63
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.bnez a1, .LBB7_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB7_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_medium_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -63
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB7_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB7_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, -63
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -131,14 +232,27 @@ define i32 @ne_medium_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <ne_medium_bedge_pos>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_medium_bedge_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x7ff
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_medium_bedge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_medium_bedge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, -2047
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.bnez a1, .LBB8_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB8_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_medium_bedge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 2047
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB8_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB8_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, 2047
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -146,36 +260,85 @@ define i32 @ne_medium_bedge_pos(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm), negative value fit in 12 bit too.
-; RV32IFDC-LABEL: <ne_medium_bedge_neg>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <ne_medium_bedge_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x7ff
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @ne_medium_bedge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_medium_bedge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, 2047
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.bnez a1, .LBB9_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB9_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_medium_bedge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -2047
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB9_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB9_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, -2047
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is big and do not fit in 12 bit (imm), fit in i32
-; RV32IFDC-LABEL: <ne_big_ledge_pos>:
-; RV32IFDC-NOT: [[COND:c.b.*]]
-; --- no compress extension
-; nothing to check.
define i32 @ne_big_ledge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_big_ledge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a0, 1
+; RV32IFDC-NEXT: slli a2, a0, 11
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: bne a1, a2, .LBB10_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB10_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_big_ledge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a0, zero, 1
+; RV32IFD-NEXT: slli a2, a0, 11
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB10_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB10_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, 2048
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is big and do not fit in 12 bit (imm), fit in i32
-; RV32IFDC-LABEL: <ne_big_ledge_neg>:
-; RV32IFDC-NOT: [[COND:c.b.*]]
-; --- no compress extension
-; nothing to check.
define i32 @ne_big_ledge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: ne_big_ledge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: addi a2, zero, -2048
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: bne a1, a2, .LBB11_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB11_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: ne_big_ledge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -2048
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: bne a1, a2, .LBB11_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB11_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp ne i32 %in0, -2048
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -185,56 +348,112 @@ define i32 @ne_big_ledge_neg(i32 %in0) minsize {
;; Same as above, but for eq
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <eq_small_pos>:
-; RV32IFDC: c.li [[REG:.*]], 0x14
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_small_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x14
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_small_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_small_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, 20
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: beq a1, a2, .LBB12_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB12_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_small_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 20
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB12_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB12_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, 20
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <eq_small_neg>:
-; RV32IFDC: c.li [[REG:.*]], -0x14
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_small_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x14
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_small_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_small_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, -20
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: beq a1, a2, .LBB13_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB13_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_small_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -20
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB13_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB13_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, -20
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <eq_small_edge_pos>:
-; RV32IFDC: c.li [[REG:.*]], 0x1f
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_small_edge_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x1f
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_small_edge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_small_edge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, 31
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: beq a1, a2, .LBB14_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB14_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_small_edge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 31
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB14_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB14_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, 31
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <eq_small_edge_neg>:
-; RV32IFDC: c.li [[REG:.*]], -0x20
-; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_small_edge_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x20
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_small_edge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_small_edge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a2, -32
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: beq a1, a2, .LBB15_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB15_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_small_edge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -32
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB15_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB15_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, -32
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -242,14 +461,27 @@ define i32 @eq_small_edge_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <eq_medium_ledge_pos>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x21
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_medium_ledge_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x21
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_medium_ledge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_medium_ledge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, -33
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.beqz a1, .LBB16_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB16_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_medium_ledge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 33
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB16_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB16_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, 33
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -257,14 +489,27 @@ define i32 @eq_medium_ledge_pos(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <eq_medium_ledge_neg>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_medium_ledge_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x21
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_medium_ledge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_medium_ledge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, 33
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.beqz a1, .LBB17_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB17_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_medium_ledge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -33
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB17_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB17_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, -33
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -272,14 +517,27 @@ define i32 @eq_medium_ledge_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <eq_medium_pos>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_medium_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x3f
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_medium_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_medium_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, -63
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.beqz a1, .LBB18_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB18_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_medium_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 63
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB18_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB18_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, 63
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -287,14 +545,27 @@ define i32 @eq_medium_pos(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <eq_medium_neg>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_medium_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x3f
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_medium_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_medium_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, 63
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.beqz a1, .LBB19_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB19_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_medium_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -63
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB19_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB19_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, -63
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -302,14 +573,27 @@ define i32 @eq_medium_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <eq_medium_bedge_pos>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_medium_bedge_pos>:
-; RV32IFD: addi [[REG:.*]], zero, 0x7ff
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_medium_bedge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_medium_bedge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, -2047
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.beqz a1, .LBB20_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB20_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_medium_bedge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, 2047
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB20_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB20_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, 2047
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
@@ -317,36 +601,85 @@ define i32 @eq_medium_bedge_pos(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm), negative value fit in 12 bit too.
-; RV32IFDC-LABEL: <eq_medium_bedge_neg>:
-; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff
-; RV32IFDC: [[COND:c.*]] [[MAYZEROREG]], [[PLACE:.*]]
-; --- no compress extension
-; RV32IFD-LABEL: <eq_medium_bedge_neg>:
-; RV32IFD: addi [[REG:.*]], zero, -0x7ff
-; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @eq_medium_bedge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_medium_bedge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: addi a1, a0, 2047
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: c.beqz a1, .LBB21_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB21_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_medium_bedge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -2047
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB21_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB21_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, -2047
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is big and do not fit in 12 bit (imm), fit in i32
-; RV32IFDC-LABEL: <eq_big_ledge_pos>:
-; RV32IFDC-NOT: [[COND:c.b.*]]
-; --- no compress extension
-; nothing to check.
define i32 @eq_big_ledge_pos(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_big_ledge_pos:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: c.li a0, 1
+; RV32IFDC-NEXT: slli a2, a0, 11
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: beq a1, a2, .LBB22_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB22_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_big_ledge_pos:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a0, zero, 1
+; RV32IFD-NEXT: slli a2, a0, 11
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB22_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB22_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, 2048
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
; constant is big and do not fit in 12 bit (imm), fit in i32
-; RV32IFDC-LABEL: <eq_big_ledge_neg>:
-; RV32IFDC-NOT: [[COND:c.b.*]]
-; --- no compress extension
-; nothing to check.
define i32 @eq_big_ledge_neg(i32 %in0) minsize {
+; RV32IFDC-LABEL: eq_big_ledge_neg:
+; RV32IFDC: # %bb.0:
+; RV32IFDC-NEXT: c.mv a1, a0
+; RV32IFDC-NEXT: addi a2, zero, -2048
+; RV32IFDC-NEXT: addi a0, zero, -99
+; RV32IFDC-NEXT: beq a1, a2, .LBB23_2
+; RV32IFDC-NEXT: # %bb.1:
+; RV32IFDC-NEXT: addi a0, zero, 42
+; RV32IFDC-NEXT: .LBB23_2:
+; RV32IFDC-NEXT: c.jr ra
+;
+; RV32IFD-LABEL: eq_big_ledge_neg:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a1, a0, 0
+; RV32IFD-NEXT: addi a2, zero, -2048
+; RV32IFD-NEXT: addi a0, zero, -99
+; RV32IFD-NEXT: beq a1, a2, .LBB23_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: addi a0, zero, 42
+; RV32IFD-NEXT: .LBB23_2:
+; RV32IFD-NEXT: jalr zero, 0(ra)
%cmp = icmp eq i32 %in0, -2048
%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
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