[llvm] [DAG] Fold vecreduce.or(sext(x)) to sext(vecreduce.or(x)) (PR #108959)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon approved this pull request.

Should we be doing this in InstCombine as well? It already does this for `logic(ext(x),ext(y)) -> ext(logic(x,y))` patterns

https://github.com/llvm/llvm-project/pull/108959