[llvm] 742e04d - [X86] combineConcatVectorOps - handle *_EXTEND nodes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 17 03:40:53 PDT 2024
Author: Simon Pilgrim
Date: 2024-09-17T11:40:37+01:00
New Revision: 742e04de96d4094e7070beb9afab10279c8b179e
URL: https://github.com/llvm/llvm-project/commit/742e04de96d4094e7070beb9afab10279c8b179e
DIFF: https://github.com/llvm/llvm-project/commit/742e04de96d4094e7070beb9afab10279c8b179e.diff
LOG: [X86] combineConcatVectorOps - handle *_EXTEND nodes
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2946c2b43112b0..c12464f25db7e2 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -56929,6 +56929,23 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
}
}
break;
+ case ISD::ANY_EXTEND:
+ case ISD::SIGN_EXTEND:
+ case ISD::ZERO_EXTEND:
+ // TODO: Handle ANY_EXTEND combos with SIGN/ZERO_EXTEND.
+ if (!IsSplat && NumOps == 2 &&
+ ((VT.is256BitVector() && Subtarget.hasInt256()) ||
+ (VT.is512BitVector() && Subtarget.useAVX512Regs() &&
+ (EltSizeInBits >= 32 || Subtarget.useBWIRegs())))) {
+ EVT SrcVT = Ops[0].getOperand(0).getValueType();
+ if (SrcVT.isSimple() && SrcVT.is128BitVector() &&
+ SrcVT == Ops[1].getOperand(0).getValueType()) {
+ EVT NewSrcVT = SrcVT.getDoubleNumVectorElementsVT(Ctx);
+ return DAG.getNode(Op0.getOpcode(), DL, VT,
+ ConcatSubOperand(NewSrcVT, Ops, 0));
+ }
+ }
+ break;
case X86ISD::VSHLI:
case X86ISD::VSRLI:
// Special case: SHL/SRL AVX1 V4i64 by 32-bits can lower as a shuffle.
diff --git a/llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll b/llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
index 53de286cc5cf12..f7c29cba30bd50 100644
--- a/llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
@@ -4754,10 +4754,7 @@ define void @vec384_v12i32_to_v6i64_factor2(ptr %in.vec.base.ptr, ptr %in.vec.bi
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa (%rdi), %ymm0
; AVX512BW-NEXT: vpaddb (%rsi), %ymm0, %ymm0
-; AVX512BW-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm0
-; AVX512BW-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
; AVX512BW-NEXT: vpaddb (%rdx), %zmm0, %zmm0
; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rcx)
; AVX512BW-NEXT: vzeroupper
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