[llvm] [AMDGPU] Exclude implicit uses and defs in SIInsertWaitcnts. NFC. (PR #108953)

[Stanislav Mekhanoshin via llvm-commits]

https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/108953

Change all_uses/all_defs to uses/defs where it obviously cannot happen.

>From 40d3fa4e760b33a99df784de39018144c45524ce Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Tue, 17 Sep 2024 03:04:28 -0700
Subject: [PATCH] [AMDGPU] Exclude implicit uses and defs in SIInsertWaitcnts.
 NFC.

Change all_uses/all_defs to uses/defs where it obviously cannot
happen.
---
 llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index fd9fe1196b7853..743e4bf3d3d679 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -819,7 +819,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
                  Inst.getOpcode() != AMDGPU::DS_APPEND &&
                  Inst.getOpcode() != AMDGPU::DS_CONSUME &&
                  Inst.getOpcode() != AMDGPU::DS_ORDERED_COUNT) {
-        for (const MachineOperand &Op : Inst.all_uses()) {
+        for (const MachineOperand &Op : Inst.uses()) {
           if (Op.isReg() && TRI->isVectorRegister(*MRI, Op.getReg()))
             setExpScore(&Inst, TRI, MRI, Op, CurrScore);
         }
@@ -863,7 +863,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
         // can be used as the actual source after export patching, so
         // we need to treat them like sources and set the EXP_CNT
         // score.
-        for (MachineOperand &DefMO : Inst.all_defs()) {
+        for (MachineOperand &DefMO : Inst.defs()) {
           if (TRI->isVGPR(*MRI, DefMO.getReg())) {
             setRegScore(
                 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)),
@@ -871,7 +871,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
           }
         }
       }
-      for (const MachineOperand &Op : Inst.all_uses()) {
+      for (const MachineOperand &Op : Inst.uses()) {
         if (Op.isReg() && TRI->isVectorRegister(*MRI, Op.getReg()))
           setExpScore(&Inst, TRI, MRI, Op, CurrScore);
       }
@@ -2326,7 +2326,7 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML,
         if (MI.mayStore())
           HasVMemStore = true;
       }
-      for (const MachineOperand &Op : MI.all_uses()) {
+      for (const MachineOperand &Op : MI.uses()) {
         if (!Op.isReg() || !TRI->isVectorRegister(*MRI, Op.getReg()))
           continue;
         RegInterval Interval = Brackets.getRegInterval(&MI, MRI, TRI, Op);
@@ -2353,7 +2353,7 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML,
 
       // VMem load vgpr def
       if (isVMEMOrFlatVMEM(MI) && MI.mayLoad()) {
-        for (const MachineOperand &Op : MI.all_defs()) {
+        for (const MachineOperand &Op : MI.defs()) {
           RegInterval Interval = Brackets.getRegInterval(&MI, MRI, TRI, Op);
           for (int RegNo = Interval.first; RegNo < Interval.second; ++RegNo) {
             // If we find a register that is loaded inside the loop, 1. and 2.