[llvm] [AMDGPU] Refine operand iterators in the SIInsertWaitcnts. NFCI. (PR #108884)

[Jay Foad via llvm-commits]

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@@ -2357,41 +2326,43 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML,
         if (MI.mayStore())
           HasVMemStore = true;
       }
-      for (unsigned I = 0; I < MI.getNumOperands(); I++) {
-        MachineOperand &Op = MI.getOperand(I);
+      for (const MachineOperand &Op : MI.all_uses()) {
         if (!Op.isReg() || !TRI->isVectorRegister(*MRI, Op.getReg()))
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jayfoad wrote:

Nit: don't need the isReg check.

https://github.com/llvm/llvm-project/pull/108884