[llvm] [NewPM][CodeGen] Port MachineLICM to NPM (PR #107376)
Akshat Oke via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 16 23:47:33 PDT 2024
https://github.com/Akshat-Oke updated https://github.com/llvm/llvm-project/pull/107376
>From 67313a1158158297982b0ddc3a4b4b5d7c9c2d5f Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 5 Sep 2024 09:33:59 +0000
Subject: [PATCH 1/5] [NewPM][CodeGen] Port MachineLICM to NPM
---
llvm/include/llvm/CodeGen/MachineBasicBlock.h | 12 +-
llvm/include/llvm/CodeGen/MachineLICM.h | 33 ++++
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/MachineLICM.cpp | 174 ++++++++++++------
llvm/lib/Passes/PassBuilder.cpp | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 1 +
.../AArch64/mlicm-stack-write-check.mir | 1 +
.../CodeGen/AArch64/sme-machine-licm-vg.mir | 1 +
llvm/test/CodeGen/AMDGPU/licm-regpressure.mir | 1 +
llvm/test/CodeGen/AMDGPU/licm-valu.mir | 1 +
.../CodeGen/AMDGPU/machinelicm-convergent.mir | 1 +
.../AMDGPU/machinelicm-copy-like-instrs.mir | 1 +
.../CodeGen/AMDGPU/machinelicm-undef-use.mir | 1 +
...HoistingDueToBlockHotnessNoProfileData.mir | 18 +-
...leHoistingDueToBlockHotnessProfileData.mir | 17 +-
.../PowerPC/machinelicm-cse-dead-flag.mir | 3 +-
.../CodeGen/X86/machine-licm-vs-wineh.mir | 1 +
llvm/test/CodeGen/X86/unfoldMemoryOperand.mir | 3 +-
.../MIR/X86/mlicm-hoist-pre-regalloc.mir | 1 +
20 files changed, 206 insertions(+), 70 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/MachineLICM.h
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 6efb17c55493a9..6cf151c951b19f 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -983,6 +983,12 @@ class MachineBasicBlock
return SplitCriticalEdge(Succ, nullptr, &MFAM, LiveInSets);
}
+ // Helper method for new pass manager migration.
+ MachineBasicBlock *
+ SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P,
+ MachineFunctionAnalysisManager *MFAM,
+ std::vector<SparseBitVector<>> *LiveInSets);
+
/// Check if the edge between this block and the given successor \p
/// Succ, can be split. If this returns true a subsequent call to
/// SplitCriticalEdge is guaranteed to return a valid basic block if
@@ -1256,12 +1262,6 @@ class MachineBasicBlock
/// unless you know what you're doing, because it doesn't update Pred's
/// successors list. Use Pred->removeSuccessor instead.
void removePredecessor(MachineBasicBlock *Pred);
-
- // Helper method for new pass manager migration.
- MachineBasicBlock *
- SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P,
- MachineFunctionAnalysisManager *MFAM,
- std::vector<SparseBitVector<>> *LiveInSets);
};
raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);
diff --git a/llvm/include/llvm/CodeGen/MachineLICM.h b/llvm/include/llvm/CodeGen/MachineLICM.h
new file mode 100644
index 00000000000000..7d3cd4d5135472
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineLICM.h
@@ -0,0 +1,33 @@
+
+//===- llvm/CodeGen/MachineLICM.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINELICM_H
+#define LLVM_CODEGEN_MACHINELICM_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+template <typename DerivedT, bool PreRegAlloc>
+class MachineLICMBasePass : public PassInfoMixin<DerivedT> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+class EarlyMachineLICMPass
+ : public MachineLICMBasePass<EarlyMachineLICMPass, true> {};
+
+class MachineLICMPass : public MachineLICMBasePass<MachineLICMPass, false> {};
+
+template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
+template class MachineLICMBasePass<MachineLICMPass, false>;
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_MACHINELICM_H
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index a99fed86d168d1..13bc4700d87029 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -44,6 +44,7 @@
#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineVerifier.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 4047fd0478579f..bf3965d76c878a 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -133,6 +133,8 @@ MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass())
MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
+MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
+MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
@@ -203,7 +205,6 @@ DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass)
DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter)
DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass)
-DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass)
DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass)
DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass)
@@ -227,7 +228,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
-DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 1e4bf4bba56220..e9b4c7679f7f2f 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -15,6 +15,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
@@ -117,7 +118,7 @@ STATISTIC(NumNotHoistedDueToHotness,
namespace {
enum HoistResult { NotHoisted = 1, Hoisted = 2, ErasedMI = 4 };
- class MachineLICMBase : public MachineFunctionPass {
+ class MachineLICMImpl {
const TargetInstrInfo *TII = nullptr;
const TargetLoweringBase *TLI = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -126,6 +127,8 @@ namespace {
TargetSchedModel SchedModel;
bool PreRegAlloc = false;
bool HasProfileData = false;
+ Pass *LegacyPass;
+ MachineFunctionAnalysisManager *MFAM;
// Various analyses that we use...
AliasAnalysis *AA = nullptr; // Alias analysis info.
@@ -182,22 +185,20 @@ namespace {
unsigned SpeculationState = SpeculateUnknown;
public:
- MachineLICMBase(char &PassID, bool PreRegAlloc)
- : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<MachineLoopInfoWrapperPass>();
- if (DisableHoistingToHotterBlocks != UseBFI::None)
- AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<AAResultsWrapperPass>();
- AU.addPreserved<MachineLoopInfoWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
+ MachineLICMImpl(bool PreRegAlloc, Pass *LegacyPass,
+ MachineFunctionAnalysisManager *MFAM, AliasAnalysis *AA,
+ MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *MLI,
+ MachineDominatorTree *DT)
+ : PreRegAlloc(PreRegAlloc), LegacyPass(LegacyPass), MFAM(MFAM), AA(AA),
+ MBFI(MBFI), MLI(MLI), DT(DT) {
+ assert((LegacyPass || MFAM) && "LegacyPass or MFAM must be provided");
+ assert(!(LegacyPass && MFAM) &&
+ "LegacyPass and MFAM cannot be provided at the same time");
}
- void releaseMemory() override {
+ bool run(MachineFunction &MF);
+
+ void releaseMemory() {
RegSeen.clear();
RegPressure.clear();
RegLimit.clear();
@@ -297,6 +298,26 @@ namespace {
MachineBasicBlock *CurPreheader);
};
+ class MachineLICMBase : public MachineFunctionPass {
+ bool PreRegAlloc;
+
+ public:
+ MachineLICMBase(char &ID, bool PreRegAlloc)
+ : MachineFunctionPass(ID), PreRegAlloc(PreRegAlloc) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<MachineLoopInfoWrapperPass>();
+ if (DisableHoistingToHotterBlocks != UseBFI::None)
+ AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<AAResultsWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ };
+
class MachineLICM : public MachineLICMBase {
public:
static char ID;
@@ -343,6 +364,19 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ MachineBlockFrequencyInfo *MBFI =
+ DisableHoistingToHotterBlocks != UseBFI::None
+ ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
+ : nullptr;
+ MachineLoopInfo *MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ MachineDominatorTree *DT =
+ &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+ MachineLICMImpl Impl(PreRegAlloc, this, nullptr, AA, MBFI, MLI, DT);
+ return Impl.run(MF);
+}
+
+bool MachineLICMImpl::run(MachineFunction &MF) {
Changed = FirstInLoop = false;
const TargetSubtargetInfo &ST = MF.getSubtarget();
TII = ST.getInstrInfo();
@@ -352,6 +386,11 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
SchedModel.init(&ST);
+ // FIXME: Remove this assignment or convert to an assert?
+ // MachineLICM and PostRAMachineLICM were distinguished by introducing
+ // EarlyMachineLICM and MachineLICM respectively to avoid "using an unreliable
+ // MRI::isSSA() check to determine whether register allocation has happened"
+ // (See 4a7c8e7).
PreRegAlloc = MRI->isSSA();
HasProfileData = MF.getFunction().hasProfileData();
@@ -371,13 +410,6 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
}
- // Get our Loop information...
- if (DisableHoistingToHotterBlocks != UseBFI::None)
- MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-
if (HoistConstLoads)
InitializeLoadsHoistableLoops();
@@ -397,7 +429,7 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
CSEMap.clear();
}
}
-
+ releaseMemory();
return Changed;
}
@@ -478,7 +510,7 @@ static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
/// Examine the instruction for potential LICM candidate. Also
/// gather register def and frame object update information.
-void MachineLICMBase::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
+void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
BitVector &RUClobbers,
SmallDenseSet<int> &StoredFIs,
SmallVectorImpl<CandidateInfo> &Candidates,
@@ -573,7 +605,7 @@ void MachineLICMBase::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
/// Walk the specified region of the CFG and hoist loop invariants out to the
/// preheader.
-void MachineLICMBase::HoistRegionPostRA(MachineLoop *CurLoop,
+void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
MachineBasicBlock *Preheader = getCurPreheader(CurLoop, CurPreheader);
if (!Preheader)
@@ -675,7 +707,7 @@ void MachineLICMBase::HoistRegionPostRA(MachineLoop *CurLoop,
/// Add register 'Reg' to the livein sets of BBs in the current loop, and make
/// sure it is not killed by any instructions in the loop.
-void MachineLICMBase::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
+void MachineLICMImpl::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
if (!BB->isLiveIn(Reg))
BB->addLiveIn(Reg);
@@ -692,7 +724,7 @@ void MachineLICMBase::AddToLiveIns(MCRegister Reg, MachineLoop *CurLoop) {
/// When an instruction is found to only use loop invariant operands that is
/// safe to hoist, this instruction is called to do the dirty work.
-void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def,
+void MachineLICMImpl::HoistPostRA(MachineInstr *MI, unsigned Def,
MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
MachineBasicBlock *Preheader = getCurPreheader(CurLoop, CurPreheader);
@@ -724,7 +756,7 @@ void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def,
/// Check if this mbb is guaranteed to execute. If not then a load from this mbb
/// may not be safe to hoist.
-bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB,
+bool MachineLICMImpl::IsGuaranteedToExecute(MachineBasicBlock *BB,
MachineLoop *CurLoop) {
if (SpeculationState != SpeculateUnknown)
return SpeculationState == SpeculateFalse;
@@ -748,7 +780,7 @@ bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB,
/// virtual register uses. Even though rematerializable RA might not actually
/// rematerialize it in this scenario. In that case we do not want to hoist such
/// instruction out of the loop in a belief RA will sink it back if needed.
-bool MachineLICMBase::isTriviallyReMaterializable(
+bool MachineLICMImpl::isTriviallyReMaterializable(
const MachineInstr &MI) const {
if (!TII->isTriviallyReMaterializable(MI))
return false;
@@ -761,14 +793,14 @@ bool MachineLICMBase::isTriviallyReMaterializable(
return true;
}
-void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
+void MachineLICMImpl::EnterScope(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
// Remember livein register pressure.
BackTrace.push_back(RegPressure);
}
-void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
+void MachineLICMImpl::ExitScope(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
BackTrace.pop_back();
}
@@ -776,9 +808,10 @@ void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
/// Destroy scope for the MBB that corresponds to the given dominator tree node
/// if its a leaf or all of its children are done. Walk up the dominator tree to
/// destroy ancestors which are now done.
-void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
- DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
- const DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
+void MachineLICMImpl::ExitScopeIfDone(
+ MachineDomTreeNode *Node,
+ DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren,
+ const DenseMap<MachineDomTreeNode *, MachineDomTreeNode *> &ParentMap) {
if (OpenChildren[Node])
return;
@@ -796,7 +829,7 @@ void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
/// specified header block, and that are in the current loop) in depth first
/// order w.r.t the DominatorTree. This allows us to visit definitions before
/// uses, allowing us to hoist a loop body in one pass without iteration.
-void MachineLICMBase::HoistOutOfLoop(MachineDomTreeNode *HeaderN,
+void MachineLICMImpl::HoistOutOfLoop(MachineDomTreeNode *HeaderN,
MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
MachineBasicBlock *Preheader = getCurPreheader(CurLoop, CurPreheader);
@@ -902,7 +935,7 @@ static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
/// Find all virtual register references that are liveout of the preheader to
/// initialize the starting "register pressure". Note this does not count live
/// through (livein but not used) registers.
-void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
+void MachineLICMImpl::InitRegPressure(MachineBasicBlock *BB) {
std::fill(RegPressure.begin(), RegPressure.end(), 0);
// If the preheader has only a single predecessor and it ends with a
@@ -921,7 +954,7 @@ void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
}
/// Update estimate of register pressure after the specified instruction.
-void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
+void MachineLICMImpl::UpdateRegPressure(const MachineInstr *MI,
bool ConsiderUnseenAsDef) {
auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/true, ConsiderUnseenAsDef);
for (const auto &RPIdAndCost : Cost) {
@@ -940,7 +973,7 @@ void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
/// figure out which usages are live-ins.
/// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
DenseMap<unsigned, int>
-MachineLICMBase::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
+MachineLICMImpl::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
bool ConsiderUnseenAsDef) {
DenseMap<unsigned, int> Cost;
if (MI->isImplicitDef())
@@ -1072,7 +1105,7 @@ static bool isCopyFeedingInvariantStore(const MachineInstr &MI,
/// Returns true if the instruction may be a suitable candidate for LICM.
/// e.g. If the instruction is a call, then it's obviously not safe to hoist it.
-bool MachineLICMBase::IsLICMCandidate(MachineInstr &I, MachineLoop *CurLoop) {
+bool MachineLICMImpl::IsLICMCandidate(MachineInstr &I, MachineLoop *CurLoop) {
// Check if it's safe to move the instruction.
bool DontMoveAcrossStore = !HoistConstLoads || !AllowedToHoistLoads[CurLoop];
if ((!I.isSafeToMove(DontMoveAcrossStore)) &&
@@ -1107,7 +1140,7 @@ bool MachineLICMBase::IsLICMCandidate(MachineInstr &I, MachineLoop *CurLoop) {
}
/// Returns true if the instruction is loop invariant.
-bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I,
+bool MachineLICMImpl::IsLoopInvariantInst(MachineInstr &I,
MachineLoop *CurLoop) {
if (!IsLICMCandidate(I, CurLoop)) {
LLVM_DEBUG(dbgs() << "LICM: Instruction not a LICM candidate\n");
@@ -1118,7 +1151,7 @@ bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I,
/// Return true if the specified instruction is used by a phi node and hoisting
/// it could cause a copy to be inserted.
-bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI,
+bool MachineLICMImpl::HasLoopPHIUse(const MachineInstr *MI,
MachineLoop *CurLoop) {
SmallVector<const MachineInstr *, 8> Work(1, MI);
do {
@@ -1152,7 +1185,7 @@ bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI,
/// Compute operand latency between a def of 'Reg' and an use in the current
/// loop, return true if the target considered it high.
-bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
+bool MachineLICMImpl::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
Register Reg,
MachineLoop *CurLoop) const {
if (MRI->use_nodbg_empty(Reg))
@@ -1184,7 +1217,7 @@ bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
/// Return true if the instruction is marked "cheap" or the operand latency
/// between its def and a use is one or less.
-bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
+bool MachineLICMImpl::IsCheapInstruction(MachineInstr &MI) const {
if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
return true;
@@ -1209,9 +1242,8 @@ bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
/// Visit BBs from header to current BB, check if hoisting an instruction of the
/// given cost matrix can cause high register pressure.
-bool
-MachineLICMBase::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
- bool CheapInstr) {
+bool MachineLICMImpl::CanCauseHighRegPressure(
+ const DenseMap<unsigned, int> &Cost, bool CheapInstr) {
for (const auto &RPIdAndCost : Cost) {
if (RPIdAndCost.second <= 0)
continue;
@@ -1235,7 +1267,7 @@ MachineLICMBase::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
/// Traverse the back trace from header to the current block and update their
/// register pressures to reflect the effect of hoisting MI from the current
/// block to the preheader.
-void MachineLICMBase::UpdateBackTraceRegPressure(const MachineInstr *MI) {
+void MachineLICMImpl::UpdateBackTraceRegPressure(const MachineInstr *MI) {
// First compute the 'cost' of the instruction, i.e. its contribution
// to register pressure.
auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/false,
@@ -1249,7 +1281,7 @@ void MachineLICMBase::UpdateBackTraceRegPressure(const MachineInstr *MI) {
/// Return true if it is potentially profitable to hoist the given loop
/// invariant.
-bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI,
+bool MachineLICMImpl::IsProfitableToHoist(MachineInstr &MI,
MachineLoop *CurLoop) {
if (MI.isImplicitDef())
return true;
@@ -1375,7 +1407,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI,
/// Unfold a load from the given machineinstr if the load itself could be
/// hoisted. Return the unfolded and hoistable load, or null if the load
/// couldn't be unfolded or if it wouldn't be hoistable.
-MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI,
+MachineInstr *MachineLICMImpl::ExtractHoistableLoad(MachineInstr *MI,
MachineLoop *CurLoop) {
// Don't unfold simple loads.
if (MI->canFoldAsLoad())
@@ -1440,14 +1472,14 @@ MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI,
/// Initialize the CSE map with instructions that are in the current loop
/// preheader that may become duplicates of instructions that are hoisted
/// out of the loop.
-void MachineLICMBase::InitCSEMap(MachineBasicBlock *BB) {
+void MachineLICMImpl::InitCSEMap(MachineBasicBlock *BB) {
for (MachineInstr &MI : *BB)
CSEMap[BB][MI.getOpcode()].push_back(&MI);
}
/// Initialize AllowedToHoistLoads with information about whether invariant
/// loads can be moved outside a given loop
-void MachineLICMBase::InitializeLoadsHoistableLoops() {
+void MachineLICMImpl::InitializeLoadsHoistableLoops() {
SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
SmallVector<MachineLoop *, 8> LoopsInPreOrder;
@@ -1488,7 +1520,7 @@ void MachineLICMBase::InitializeLoadsHoistableLoops() {
/// Find an instruction amount PrevMIs that is a duplicate of MI.
/// Return this instruction if it's found.
MachineInstr *
-MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
+MachineLICMImpl::LookForDuplicate(const MachineInstr *MI,
std::vector<MachineInstr *> &PrevMIs) {
for (MachineInstr *PrevMI : PrevMIs)
if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
@@ -1501,7 +1533,7 @@ MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
/// computes the same value. If it's found, do a RAU on with the definition of
/// the existing instruction rather than hoisting the instruction to the
/// preheader.
-bool MachineLICMBase::EliminateCSE(
+bool MachineLICMImpl::EliminateCSE(
MachineInstr *MI,
DenseMap<unsigned, std::vector<MachineInstr *>>::iterator &CI) {
// Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
@@ -1566,7 +1598,7 @@ bool MachineLICMBase::EliminateCSE(
/// Return true if the given instruction will be CSE'd if it's hoisted out of
/// the loop.
-bool MachineLICMBase::MayCSE(MachineInstr *MI) {
+bool MachineLICMImpl::MayCSE(MachineInstr *MI) {
if (MI->mayLoad() && !MI->isDereferenceableInvariantLoad())
return false;
@@ -1591,7 +1623,7 @@ bool MachineLICMBase::MayCSE(MachineInstr *MI) {
/// When an instruction is found to use only loop invariant operands
/// that are safe to hoist, this instruction is called to do the dirty work.
/// It returns true if the instruction is hoisted.
-unsigned MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader,
+unsigned MachineLICMImpl::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader,
MachineLoop *CurLoop) {
MachineBasicBlock *SrcBlock = MI->getParent();
@@ -1686,7 +1718,7 @@ unsigned MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader,
/// Get the preheader for the current loop, splitting a critical edge if needed.
MachineBasicBlock *
-MachineLICMBase::getCurPreheader(MachineLoop *CurLoop,
+MachineLICMImpl::getCurPreheader(MachineLoop *CurLoop,
MachineBasicBlock *CurPreheader) {
// Determine the block to which to hoist instructions. If we can't find a
// suitable loop predecessor, we can't do any hoisting.
@@ -1704,7 +1736,8 @@ MachineLICMBase::getCurPreheader(MachineLoop *CurLoop,
return nullptr;
}
- CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), *this);
+ CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), LegacyPass,
+ MFAM, nullptr);
if (!CurPreheader) {
CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
return nullptr;
@@ -1716,7 +1749,7 @@ MachineLICMBase::getCurPreheader(MachineLoop *CurLoop,
/// Is the target basic block at least "BlockFrequencyRatioThreshold"
/// times hotter than the source basic block.
-bool MachineLICMBase::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
+bool MachineLICMImpl::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
MachineBasicBlock *TgtBlock) {
// Parse source and target basic block frequency from MBFI
uint64_t SrcBF = MBFI->getBlockFreq(SrcBlock).getFrequency();
@@ -1731,3 +1764,28 @@ bool MachineLICMBase::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
// Compare the block frequency ratio with the threshold
return Ratio > BlockFrequencyRatioThreshold;
}
+
+template <typename DerivedT, bool PreRegAlloc>
+PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
+ MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) {
+ if (MF.getFunction().hasOptNone())
+ return PreservedAnalyses::all();
+
+ auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager();
+
+ auto *DT = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ auto *MLI = &MFAM.getResult<MachineLoopAnalysis>(MF);
+ auto *MBFI = DisableHoistingToHotterBlocks != UseBFI::None
+ ? &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF)
+ : nullptr;
+ auto *AA = &FAM.getResult<AAManager>(MF.getFunction());
+
+ bool Changed =
+ MachineLICMImpl(PreRegAlloc, nullptr, &MFAM, AA, MBFI, MLI, DT).run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserve<MachineLoopAnalysis>();
+ return PA;
+}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 0d63ed22dbbf07..402b2340e5c35f 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -103,6 +103,7 @@
#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachinePassManager.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index f860b139945122..0e1bd6ba2b3b36 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -53,6 +53,7 @@
#include "llvm/CodeGen/GlobalISel/Localizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
+#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetPassConfig.h"
diff --git a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
index 0b1fdf9c33d66c..51bc77d405b94b 100644
--- a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
+++ b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64 -run-pass machinelicm -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes machinelicm -o - %s | FileCheck %s
---
name: test
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir b/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir
index e6cce9af0daf0e..31481c925ca790 100644
--- a/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir
+++ b/llvm/test/CodeGen/AArch64/sme-machine-licm-vg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=early-machinelicm %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -passes=early-machinelicm %s -o - | FileCheck %s
---
name: test_should_hoist_pfalse
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir b/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
index e818eaf95aee33..e63009fdcb43cf 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass machinelicm -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes machinelicm -o - %s | FileCheck -check-prefix=GCN %s
# MachineLICM shall limit hoisting of V_CVT instructions out of the loop keeping
# register pressure within the budget. VGPR budget at occupancy 10 is 24 vgprs.
diff --git a/llvm/test/CodeGen/AMDGPU/licm-valu.mir b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
index 00a5a4f1b32ea4..b4f5e057f532b5 100644
--- a/llvm/test/CodeGen/AMDGPU/licm-valu.mir
+++ b/llvm/test/CodeGen/AMDGPU/licm-valu.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machinelicm -o - %s | FileCheck -check-prefix=GCN %s
---
name: hoist_move
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
index e4ba07834405ac..9dc44c6e195e4c 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass=early-machinelicm -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes=early-machinelicm -o - %s | FileCheck %s
# Test to check machine LICM does not hoist convergent instructions,
# DS_PERMUTE_B32 in this example.
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
index e9945f005d2645..9465cc03209060 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgcn -run-pass=early-machinelicm -simplify-mir -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -passes=early-machinelicm -simplify-mir -o - %s | FileCheck %s
# Test to check machine LICM does not hoist convergent instructions,
# DS_PERMUTE_B32 in this example.
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
index 07eaa9f95604d0..bdd08af1c7e160 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=early-machinelicm %s -o - | FileCheck %s
# Issue #100115: test that MachineLICM does not assert on the undef use operand
# of the REG_SEQUENCE instruction.
diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
index 9706873dc37fd6..d3d3b194b3ce57 100644
--- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
+++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
@@ -16,7 +16,23 @@
# RUN: -verify-machineinstrs -disable-hoisting-to-hotter-blocks=none \
# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
# RUN: --check-prefix=CHECK-HOIST
-
+# Tests for new pass manager
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=all \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-NO-HOIST
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=all \
+# RUN: -block-freq-ratio-threshold=100000000 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=pgo \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=none \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
--- |
target datalayout = "e-m:e-i64:64-n32:64"
diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
index 88ee6633c15feb..e8ad54b9c6cd46 100644
--- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
+++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
@@ -15,7 +15,22 @@
# RUN: -disable-hoisting-to-hotter-blocks=none \
# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
# RUN: --check-prefix=CHECK-HOIST
-
+# Tests for the new pass manager
+# RUN: llc -passes early-machinelicm \
+# RUN: -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=pgo \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-NO-HOIST
+# RUN: llc -passes early-machinelicm \
+# RUN: -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=pgo \
+# RUN: -block-freq-ratio-threshold=100000000 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
+# RUN: llc -passes early-machinelicm \
+# RUN: -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: -disable-hoisting-to-hotter-blocks=none \
+# RUN: -block-freq-ratio-threshold=100 %s -o - | FileCheck %s \
+# RUN: --check-prefix=CHECK-HOIST
--- |
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
index 17913594003f51..462f5c74451e6a 100644
--- a/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
+++ b/llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
@@ -1,7 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
----
+# RUN: llc -passes early-machinelicm -mtriple=powerpc64le-unknown-linux-gnu \
+# RUN: %s -o - | FileCheck %s
name: deadFlagAfterCSE
# This case tests that after the dead %3 is CSE-ed with hoisted %5 in MachineLICM
# pass, the dead flag will be cleared for %3 if %5 has users.
diff --git a/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir b/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir
index 4bfd749fb77235..3582b178869c4d 100644
--- a/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir
+++ b/llvm/test/CodeGen/X86/machine-licm-vs-wineh.mir
@@ -1,4 +1,5 @@
# RUN: llc -o - %s -mtriple=x86_64-pc-windows-msvc -run-pass=machinelicm | FileCheck %s
+# RUN: llc -o - %s -mtriple=x86_64-pc-windows-msvc -passes=machinelicm | FileCheck %s
#
# This test checks that MachineLICM doesn't hoist loads out of funclets.
# Manually modified from the IR of the following C++ function by running
diff --git a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
index af57d972f22468..ff3d9ca378dbd5 100644
--- a/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
+++ b/llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-- -run-pass machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-- -passes machinelicm -mcpu=skx -verify-machineinstrs -o - %s | FileCheck %s
--- |
@x = dso_local global i32 0, align 4
@z = dso_local local_unnamed_addr global [1024 x i32] zeroinitializer, align 16
diff --git a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
index 90a6abdf9bd0b3..d4d59e14724ebe 100644
--- a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
@@ -1,5 +1,6 @@
--- |
; RUN: llc -run-pass=machinelicm -o - %s | FileCheck %s
+ ; RUN: llc -passes=machinelicm -o - %s | FileCheck %s
; Line numbers should not be retained when loop invariant instructions are hoisted.
; Doing so causes poor stepping bevavior.
;
>From a6c5f069efa7d81bdabf0c9391973f08014a1ece Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Fri, 6 Sep 2024 09:42:41 +0000
Subject: [PATCH 2/5] [comment-update] Move explicit instantiation
---
llvm/include/llvm/CodeGen/MachineLICM.h | 5 +++--
llvm/lib/CodeGen/MachineLICM.cpp | 5 ++++-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineLICM.h b/llvm/include/llvm/CodeGen/MachineLICM.h
index 7d3cd4d5135472..ac5b50858bbda6 100644
--- a/llvm/include/llvm/CodeGen/MachineLICM.h
+++ b/llvm/include/llvm/CodeGen/MachineLICM.h
@@ -20,13 +20,14 @@ class MachineLICMBasePass : public PassInfoMixin<DerivedT> {
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
+
class EarlyMachineLICMPass
: public MachineLICMBasePass<EarlyMachineLICMPass, true> {};
class MachineLICMPass : public MachineLICMBasePass<MachineLICMPass, false> {};
-template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
-template class MachineLICMBasePass<MachineLICMPass, false>;
+extern template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
+extern template class MachineLICMBasePass<MachineLICMPass, false>;
} // namespace llvm
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index e9b4c7679f7f2f..dc498b0c25bcc0 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -386,7 +386,7 @@ bool MachineLICMImpl::run(MachineFunction &MF) {
MRI = &MF.getRegInfo();
SchedModel.init(&ST);
- // FIXME: Remove this assignment or convert to an assert?
+ // FIXME: Remove this assignment or convert to an assert? (dead variable PreRegAlloc)
// MachineLICM and PostRAMachineLICM were distinguished by introducing
// EarlyMachineLICM and MachineLICM respectively to avoid "using an unreliable
// MRI::isSSA() check to determine whether register allocation has happened"
@@ -1765,6 +1765,9 @@ bool MachineLICMImpl::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
return Ratio > BlockFrequencyRatioThreshold;
}
+template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
+template class MachineLICMBasePass<MachineLICMPass, false>;
+
template <typename DerivedT, bool PreRegAlloc>
PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) {
>From 7520d709c427ae63c7af5722476c41bc35fe8c83 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Fri, 6 Sep 2024 10:41:43 +0000
Subject: [PATCH 3/5] Get all analyses in Impl::run and not pass them in
---
llvm/include/llvm/CodeGen/MachineLICM.h | 3 --
llvm/lib/CodeGen/MachineLICM.cpp | 50 +++++++++++--------------
2 files changed, 22 insertions(+), 31 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineLICM.h b/llvm/include/llvm/CodeGen/MachineLICM.h
index ac5b50858bbda6..686d6257d5b182 100644
--- a/llvm/include/llvm/CodeGen/MachineLICM.h
+++ b/llvm/include/llvm/CodeGen/MachineLICM.h
@@ -26,9 +26,6 @@ class EarlyMachineLICMPass
class MachineLICMPass : public MachineLICMBasePass<MachineLICMPass, false> {};
-extern template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
-extern template class MachineLICMBasePass<MachineLICMPass, false>;
-
} // namespace llvm
#endif // LLVM_CODEGEN_MACHINELICM_H
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index dc498b0c25bcc0..0b33b5b822cade 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -186,11 +186,8 @@ namespace {
public:
MachineLICMImpl(bool PreRegAlloc, Pass *LegacyPass,
- MachineFunctionAnalysisManager *MFAM, AliasAnalysis *AA,
- MachineBlockFrequencyInfo *MBFI, MachineLoopInfo *MLI,
- MachineDominatorTree *DT)
- : PreRegAlloc(PreRegAlloc), LegacyPass(LegacyPass), MFAM(MFAM), AA(AA),
- MBFI(MBFI), MLI(MLI), DT(DT) {
+ MachineFunctionAnalysisManager *MFAM)
+ : PreRegAlloc(PreRegAlloc), LegacyPass(LegacyPass), MFAM(MFAM) {
assert((LegacyPass || MFAM) && "LegacyPass or MFAM must be provided");
assert(!(LegacyPass && MFAM) &&
"LegacyPass and MFAM cannot be provided at the same time");
@@ -364,19 +361,27 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
- MachineBlockFrequencyInfo *MBFI =
- DisableHoistingToHotterBlocks != UseBFI::None
- ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
- : nullptr;
- MachineLoopInfo *MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- MachineDominatorTree *DT =
- &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
- MachineLICMImpl Impl(PreRegAlloc, this, nullptr, AA, MBFI, MLI, DT);
+ MachineLICMImpl Impl(PreRegAlloc, this, nullptr);
return Impl.run(MF);
}
+#define GET_RESULT(RESULT, GETTER, INFIX) \
+ ((LegacyPass) \
+ ? &LegacyPass->getAnalysis<RESULT##INFIX##WrapperPass>().GETTER() \
+ : &MFAM->getResult<RESULT##Analysis>(MF))
+
bool MachineLICMImpl::run(MachineFunction &MF) {
+ AA = MFAM != nullptr
+ ? &MFAM->getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager()
+ .getResult<AAManager>(MF.getFunction())
+ : &LegacyPass->getAnalysis<AAResultsWrapperPass>().getAAResults();
+ DT = GET_RESULT(MachineDominatorTree, getDomTree, );
+ MLI = GET_RESULT(MachineLoop, getLI, Info);
+ MBFI = DisableHoistingToHotterBlocks != UseBFI::None
+ ? GET_RESULT(MachineBlockFrequency, getMBFI, Info)
+ : nullptr;
+
Changed = FirstInLoop = false;
const TargetSubtargetInfo &ST = MF.getSubtarget();
TII = ST.getInstrInfo();
@@ -1765,8 +1770,8 @@ bool MachineLICMImpl::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
return Ratio > BlockFrequencyRatioThreshold;
}
-template class MachineLICMBasePass<EarlyMachineLICMPass, true>;
-template class MachineLICMBasePass<MachineLICMPass, false>;
+template class llvm::MachineLICMBasePass<EarlyMachineLICMPass, true>;
+template class llvm::MachineLICMBasePass<MachineLICMPass, false>;
template <typename DerivedT, bool PreRegAlloc>
PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
@@ -1774,18 +1779,7 @@ PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
if (MF.getFunction().hasOptNone())
return PreservedAnalyses::all();
- auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
- .getManager();
-
- auto *DT = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
- auto *MLI = &MFAM.getResult<MachineLoopAnalysis>(MF);
- auto *MBFI = DisableHoistingToHotterBlocks != UseBFI::None
- ? &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF)
- : nullptr;
- auto *AA = &FAM.getResult<AAManager>(MF.getFunction());
-
- bool Changed =
- MachineLICMImpl(PreRegAlloc, nullptr, &MFAM, AA, MBFI, MLI, DT).run(MF);
+ bool Changed = MachineLICMImpl(PreRegAlloc, nullptr, &MFAM).run(MF);
if (!Changed)
return PreservedAnalyses::all();
auto PA = getMachineFunctionPassPreservedAnalyses();
>From 6265d4cb83fe511acb53db8c9a3c193f753ed199 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Mon, 16 Sep 2024 09:38:32 +0000
Subject: [PATCH 4/5] Apply suggestions
---
llvm/include/llvm/CodeGen/MachineLICM.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/MachineLICM.h b/llvm/include/llvm/CodeGen/MachineLICM.h
index 686d6257d5b182..a4078b55353bbd 100644
--- a/llvm/include/llvm/CodeGen/MachineLICM.h
+++ b/llvm/include/llvm/CodeGen/MachineLICM.h
@@ -1,4 +1,3 @@
-
//===- llvm/CodeGen/MachineLICM.h -------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -28,4 +27,8 @@ class MachineLICMPass : public MachineLICMBasePass<MachineLICMPass, false> {};
} // namespace llvm
+extern template class llvm::MachineLICMBasePass<llvm::EarlyMachineLICMPass,
+ true>;
+extern template class llvm::MachineLICMBasePass<llvm::MachineLICMPass, false>;
+
#endif // LLVM_CODEGEN_MACHINELICM_H
>From 5ef4475951a38aff8a154a80cc17b365e487b296 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Tue, 17 Sep 2024 06:25:11 +0000
Subject: [PATCH 5/5] Move explicit instantiation
---
llvm/lib/CodeGen/MachineLICM.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 0b33b5b822cade..6768eeeb4364c8 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -1770,9 +1770,6 @@ bool MachineLICMImpl::isTgtHotterThanSrc(MachineBasicBlock *SrcBlock,
return Ratio > BlockFrequencyRatioThreshold;
}
-template class llvm::MachineLICMBasePass<EarlyMachineLICMPass, true>;
-template class llvm::MachineLICMBasePass<MachineLICMPass, false>;
-
template <typename DerivedT, bool PreRegAlloc>
PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) {
@@ -1786,3 +1783,6 @@ PreservedAnalyses MachineLICMBasePass<DerivedT, PreRegAlloc>::run(
PA.preserve<MachineLoopAnalysis>();
return PA;
}
+
+template class llvm::MachineLICMBasePass<EarlyMachineLICMPass, true>;
+template class llvm::MachineLICMBasePass<MachineLICMPass, false>;
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