[llvm] 30d7dcc - [RISCV] Add asserts requirement to loop vectorizer tests
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 16 23:19:48 PDT 2024
Author: Luke Lau
Date: 2024-09-17T14:18:36+08:00
New Revision: 30d7dcc1db476b828d3b0a7b5c9bcfbe5bd5f216
URL: https://github.com/llvm/llvm-project/commit/30d7dcc1db476b828d3b0a7b5c9bcfbe5bd5f216
DIFF: https://github.com/llvm/llvm-project/commit/30d7dcc1db476b828d3b0a7b5c9bcfbe5bd5f216.diff
LOG: [RISCV] Add asserts requirement to loop vectorizer tests
Hopefully this fixes a buildbot failure on fuchsia where opt doesn't
have -debug-only
Added:
Modified:
llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
index 89514431278a74..71ee00fbf3ec5f 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfbfmin -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
index ceedcfba4691e1..c58307d9607869 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
@@ -1,3 +1,4 @@
+; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfh -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFH
; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfhmin -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFHMIN
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