[llvm] [RISCV] Account for zvfhmin and zvfbfmin promotion in register usage (PR #108370)

[Craig Topper via llvm-commits]

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+; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfbfmin -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s
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topperc wrote:

Need `REQUIRES: asserts`

https://github.com/llvm/llvm-project/pull/108370